CNOT Oriented Synthesis for Small-Scale Boolean Functions Using Spatial Structures of Parallelotopes

• URL: http://arxiv.org/abs/2509.01912v2
• Date: Wed, 03 Sep 2025 03:10:19 GMT
• Title: CNOT Oriented Synthesis for Small-Scale Boolean Functions Using Spatial Structures of Parallelotopes
• Authors: Qiang Zheng, Yongzhen Xu, Jiaxi Zhang, Zhaofeng Su, Shenggen Zheng,
• Abstract summary: In the Noisy Intermediate-Scale Quantum (NISQ) era, quantum circuit scalability remains limited by gate fidelity and qubit counts.<n>We propose the Spatial Structure-based Hypercube Reduction(SSHR), a novel synthesis method tailored for small-scale Boolean functions.<n>Our approach outperforms existing techniques in small-scale circuit synthesis, achieving 56% and 81% reductions in CNOT gate counts.
• Score: 2.5255874956844933
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Quantum computing has garnered significant interest for its potential to achieve exponential speedups over classical approaches. However, in the Noisy Intermediate-Scale Quantum (NISQ) era, quantum circuit scalability remains limited by gate fidelity and qubit counts, restricting physical implementations to small-scale circuits. While prior work has explored logic network structures for quantum circuit synthesis, these methods often neglect the spatial structure intrinsic to Boolean functions. In this paper, we leverage this spatial structure, encoded by parallelotopes embedded in the hypercube defined by the Boolean function, to access a broader optimization space, enhancing synthesis efficiency and reducing circuit complexity. We propose the Spatial Structure-based Hypercube Reduction~(SSHR), a novel synthesis method tailored for small-scale Boolean functions ($\leq 8$). SSHR extracts global spatial features to minimize the use of Multi-Control Toffoli (MCT) gates. To further exploit spatial correlations, we introduce two variants: SSHR-H employs heuristic functions to accelerate synthesis runtime, while SSHR-I integrates an Integer Linear Programming (ILP) solver to maximize spatial structure utilization. Our approach outperforms existing techniques in small-scale circuit synthesis, achieving 56\% and 81\% reductions in CNOT gate counts compared to the Exclusive Sum-of-Products (ESOP) and Xor-And-Inverter Graph (XAG) methods, respectively.

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