Real-time decoding of the gross code memory with FPGAs

• URL: http://arxiv.org/abs/2510.21600v1
• Date: Fri, 24 Oct 2025 16:03:07 GMT
• Title: Real-time decoding of the gross code memory with FPGAs
• Authors: Thilo Maurer, Markus Bühler, Michael Kröner, Frank Haverkamp, Tristan Müller, Drew Vandeth, Blake R. Johnson,
• Abstract summary: We introduce a prototype FPGA decoder implementing the recently discovered Relay-BP algorithm.<n>The decoder is both fast and accurate, achieving a belief propagation time of 24ns.
• Score: 0.0
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: We introduce a prototype FPGA decoder implementing the recently discovered Relay-BP algorithm and targeting memory experiments on the $[[144,12,12]]$ bivariate bicycle quantum low-density parity check code. The decoder is both fast and accurate, achieving a belief propagation iteration time of 24ns. It matches the logical error performance of a floating-point implementation despite using reduced precision arithmetic. This speed is sufficient for an average per cycle decoding time under $1\,\mathrm{\mu s}$ assuming circuit model error probabilities are less than $3 \times 10^{-3}$. This prototype decoder offers useful insights on the path toward decoding solutions for scalable fault-tolerant quantum computers.

Related papers

• Decoding Correlated Errors in Quantum LDPC Codes [41.04211723135311]
  We introduce a decoding framework for correlated errors in quantum LDPC codes under circuit-level noise.<n>The core of our approach is a graph augmentation and rewiring for interference (GARI) method, which modifies the correlated detector error model.<n>Preliminary FPGA implementation results show that such high accuracy can be achieved in real time, with a per-round average decoding latency of 273 ns and sub-microsecond latency in 99.99% of the decoding instances.
  arXiv  Detail & Related papers  (2025-10-15T19:59:05Z)
• Machine Learning Decoding of Circuit-Level Noise for Bivariate Bicycle Codes [0.42542143904778074]
  We present a recurrent, transformer-based neural network designed to decode circuit-level noise on Bi Bicycle (BB) codes.<n>For the $[[72,12,6]]$ BB code, at a physical error rate of $p=0.1%$, our model achieves a logical error rate almost $5$ times lower than belief propagation.<n>These results demonstrate that machine learning decoders can out-perform conventional decoders on QLDPC codes.
  arXiv  Detail & Related papers  (2025-04-17T15:57:16Z)
• Demonstrating real-time and low-latency quantum error correction with superconducting qubits [52.08698178354922]
  We demonstrate low-latency feedback with a scalable FPGA decoder integrated into a superconducting quantum processor. We observe logical error suppression as the number of decoding rounds is increased. The decoder throughput and latency developed in this work, combined with continued device improvements, unlock the next generation of experiments.
  arXiv  Detail & Related papers  (2024-10-07T17:07:18Z)
• Quantum error correction below the surface code threshold [107.92016014248976]
  Quantum error correction provides a path to reach practical quantum computing by combining multiple physical qubits into a logical qubit. We present two surface code memories operating below a critical threshold: a distance-7 code and a distance-5 code integrated with a real-time decoder. Our results present device performance that, if scaled, could realize the operational requirements of large scale fault-tolerant quantum algorithms.
  arXiv  Detail & Related papers  (2024-08-24T23:08:50Z)
• Ambiguity Clustering: an accurate and efficient decoder for qLDPC codes [0.0]
  We introduce the Ambiguity Clustering decoder (AC) which divides measurement data into clusters that can be decoded independently.<n>With 0.3% circuit-level depolarising noise, AC is up to 27x faster than BP-OSD with matched accuracy.<n>Our implementation decodes the 144-qubit Gross code in 135us per round of syndrome extraction on an M2 CPU.
  arXiv  Detail & Related papers  (2024-06-20T17:39:31Z)
• FPGA-based Distributed Union-Find Decoder for Surface Codes [3.780617572622938]
  A fault-tolerant quantum computer must decode and correct errors faster than they appear to prevent exponential slowdown due to error correction. We report a distributed version of the Union-Find decoder that exploits parallel computing resources for further speedup.
  arXiv  Detail & Related papers  (2024-03-20T13:36:59Z)
• Estimating the Decoding Failure Rate of Binary Regular Codes Using Iterative Decoding [84.0257274213152]
  We propose a new technique to provide accurate estimates of the DFR of a two-iterations (parallel) bit flipping decoder.<n>We validate our results, providing comparisons of the modeled and simulated weight of the syndrome, incorrectly-guessed error bit distribution at the end of the first iteration, and two-itcrypteration Decoding Failure Rates (DFR)
  arXiv  Detail & Related papers  (2024-01-30T11:40:24Z)
• Scalable Quantum Error Correction for Surface Codes using FPGA [67.74017895815125]
  A fault-tolerant quantum computer must decode and correct errors faster than they appear. We report a distributed version of the Union-Find decoder that exploits parallel computing resources for further speedup. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure.
  arXiv  Detail & Related papers  (2023-01-20T04:23:00Z)
• Rapid Person Re-Identification via Sub-space Consistency Regularization [51.76876061721556]
  Person Re-Identification (ReID) matches pedestrians across disjoint cameras. Existing ReID methods adopting real-value feature descriptors have achieved high accuracy, but they are low in efficiency due to the slow Euclidean distance computation. We propose a novel Sub-space Consistency Regularization (SCR) algorithm that can speed up the ReID procedure by 0.25$ times.
  arXiv  Detail & Related papers  (2022-07-13T02:44:05Z)
• Exponential suppression of bit or phase flip errors with repetitive error correction [56.362599585843085]
  State-of-the-art quantum platforms typically have physical error rates near $10-3$. Quantum error correction (QEC) promises to bridge this divide by distributing quantum logical information across many physical qubits. We implement 1D repetition codes embedded in a 2D grid of superconducting qubits which demonstrate exponential suppression of bit or phase-flip errors.
  arXiv  Detail & Related papers  (2021-02-11T17:11:20Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.