Delay Time Characterization on FPGA: A Low Nonlinearity, Picosecond Resolution Time-to-Digital Converter on 16-nm FPGA using Bin Sequence Calibration

• URL: http://arxiv.org/abs/2511.05583v1
• Date: Wed, 05 Nov 2025 09:29:39 GMT
• Title: Delay Time Characterization on FPGA: A Low Nonlinearity, Picosecond Resolution Time-to-Digital Converter on 16-nm FPGA using Bin Sequence Calibration
• Authors: Sunwoo Park, Byungkwon Park, Eunsung Kim, Jiwon Yune, Seungho Han, Seunggo Nam,
• Abstract summary: This work introduces two novel hardware-independent post-processing techniques that significantly enhance the performance of FPGA-based TDCs.<n>POR and ITI address the missing code problem by inferring the partial order of each time bin through code density test data.<n>ITI further improves fine time resolution by merging multiple calibrated tapped delay lines (TDLs) into a single unified delay chain.
• Score: 1.9211034400077684
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: We present a Time-to-Digital Converter (TDC) implemented on a 16 nm Xilinx UltraScale Plus FPGA that achieves a resolution of 1.15 ps, RMS precision of 3.38 ps, a differential nonlinearity (DNL) of [-0.43, 0.24] LSB, and an integral nonlinearity (INL) of [-2.67, 0.15] LSB. This work introduces two novel hardware-independent post-processing techniques - Partial Order Reconstruction (POR) and Iterative Time-bin Interleaving (ITI) - that significantly enhance the performance of FPGA-based TDCs. POR addresses the missing code problem by inferring the partial order of each time bin through code density test data and directed acyclic graph (DAG) analysis, enabling near-complete recovery of usable bins. ITI further improves fine time resolution by merging multiple calibrated tapped delay lines (TDLs) into a single unified delay chain, achieving scalable resolution without resorting to averaging. Compared to state-of-the-art FPGA-based TDC architectures, the proposed methods deliver competitive or superior performance with reduced hardware overhead. These techniques are broadly applicable to high-resolution time measurement and precise delay calibration in programmable logic platforms.

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