Addressable fault-tolerant universal quantum gate operations for high-rate lift-connected surface codes

• URL: http://arxiv.org/abs/2511.10191v1
• Date: Fri, 14 Nov 2025 01:37:59 GMT
• Title: Addressable fault-tolerant universal quantum gate operations for high-rate lift-connected surface codes
• Authors: Josias Old, Juval Bechar, Markus Müller, Sascha Heußen,
• Abstract summary: Quantum low-density parity check (qLDPC) codes are among the leading candidates to realize error-corrected quantum memories with low qubit overhead.<n>In this work, we introduce a construction to implement all Clifford quantum gate operations on the recently introduced lift-connected surface (LCS) codes.
• Score: 0.8919684307774216
• License: http://creativecommons.org/licenses/by-nc-nd/4.0/
• Abstract: Quantum low-density parity check (qLDPC) codes are among the leading candidates to realize error-corrected quantum memories with low qubit overhead. Potentially high encoding rates and large distance relative to their block size make them appealing for practical suppression of noise in near-term quantum computers. In addition to increased qubit-connectivity requirements compared to more conventional topological quantum error correcting codes, qLDPC codes remain notoriously hard to compute with. In this work, we introduce a construction to implement all Clifford quantum gate operations on the recently introduced lift-connected surface (LCS) codes (Old et al. 2024). These codes can be implemented in a 3D-local architecture and achieve asymptotic scaling $[[n, \mathcal{O}(n^{1/3}), \mathcal{O}(n^{1/3})]]$. In particular, LCS codes realize favorable instances with small numbers of qubits: For the $[[15,3,3]]$ LCS code, we provide deterministic fault-tolerant (FT) circuits of the logical gate set $\{\overline{H}_i, \overline{H}_i, \overline{C_i X_j}\}_{i,j \in (0,1,2)}$ based on flag qubits. By adding a procedure for FT magic state preparation, we show quantitatively how to realize an FT universal gate set in $d=3$ LCS codes. Numerical simulations indicate that our gate constructions can attain pseudothresholds in the range $p_{\mathrm{th}} \approx 4.8\cdot 10^{-3}-1.2\cdot 10^{-2}$ for circuit-level noise. The schemes use a moderate number of qubits and are therefore feasible for near-term experiments, facilitating progress for fault-tolerant error corrected logic in high-rate qLPDC codes.

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