GNN-based Path-aware multi-view Circuit Learning for Technology Mapping

• URL: http://arxiv.org/abs/2601.14286v1
• Date: Wed, 14 Jan 2026 02:15:48 GMT
• Title: GNN-based Path-aware multi-view Circuit Learning for Technology Mapping
• Authors: Wentao Jiang, Jingxin Wang, Zhang Hu, Zhengyuan Shi, Chengyu Ma, Qiang Xu, Weikang Qian, Zhufei Chu,
• Abstract summary: We introduce GPA(graph neural network (GNN)-based Path-Aware multi-view circuit learning), a novel GNN framework that learns precise, data-driven delay predictions.<n> GPA achieves 19.9%, 2.1% and 4.1% average delay reduction over the conventionalgnostics methods.
• Score: 8.368416885163859
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic delay models that fail to capture the nuanced timing behavior behavior of real post-mapping circuits. To address this fundamental limitation, we introduce GPA(graph neural network (GNN)-based Path-Aware multi-view circuit learning), a novel GNN framework that learns precise, data-driven delay predictions by synergistically fusing three complementary views of circuit structure: And-Inverter Graphs (AIGs)-based functional encoding, post-mapping technology emphasizes critical timing paths. Trained exclusively on real cell delays extracted from critical paths of industrial-grade post-mapping netlists, GPA learns to classify cut delays with unprecedented accuracy, directly informing smarter mapping decisions. Evaluated on the 19 EPFL combinational benchmarks, GPA achieves 19.9%, 2.1% and 4.1% average delay reduction over the conventional heuristics methods (techmap, MCH) and the prior state-of-the-art ML-based approach SLAP, respectively-without compromising area efficiency.

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