Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms
- URL: http://arxiv.org/abs/2601.22804v1
- Date: Fri, 30 Jan 2026 10:33:39 GMT
- Title: Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms
- Authors: Rourab Paul, Krishnendu Guha, Amlan Chakrabarti,
- Abstract summary: Number Theoretic Transform (NTT) is the most essential component for multiplications used in lattice-based Post-Quantum Cryptography (PQC) algorithms.<n>Side-channel attacks (SCA) and hardware vulnerabilities in the form of hardware Trojans may alter control signals to disrupt the circuit's control flow.<n>We present a secure NTT architecture capable of detecting unconventional delays, control-flow disruptions, and SASCA.
- Score: 2.5909615773091526
- License: http://creativecommons.org/licenses/by/4.0/
- Abstract: Number Theoretic Transform (NTT) is the most essential component for polynomial multiplications used in lattice-based Post-Quantum Cryptography (PQC) algorithms such as Kyber, Dilithium, NTRU etc. However, side-channel attacks (SCA) and hardware vulnerabilities in the form of hardware Trojans may alter control signals to disrupt the circuit's control flow and introduce unconventional delays in the critical hardware of PQC. Hardware Trojans, especially on control signals, are more low cost and impactful than data signals because a single corrupted control signal can disrupt or bypass entire computation sequences, whereas data faults usually cause only localized errors. On the other hand, adversaries can perform Soft Analytical Side Channel Attacks (SASCA) on the design using the inserted hardware Trojan. In this paper, we present a secure NTT architecture capable of detecting unconventional delays, control-flow disruptions, and SASCA, while providing an adaptive fault-correction methodology for their mitigation. Extensive simulations and implementations of our Secure NTT on Artix-7 FPGA with different Kyber variants show that our fault detection and correction modules can efficiently detect and correct faults whether caused unintentionally or intentionally by hardware Trojans with a high success rate, while introducing only modest area and time overheads.
Related papers
- Boosting Device Utilization in Control Flow Auditing [47.36491265793223]
Control Flow (CFAud) is a mechanism wherein a remote verifier (Vrf) is guaranteed to received evidence about the control flow path taken on a prover (Prv) MCU, even when Prv software is compromised.<n>Current CFAud requires a busy-wait'' phase where root-of-anchored root-of-RoT in Prv retains execution to ensure delivery of flow evidence to Vrf.<n>CARAMEL is a hardware RoT co-design that enables Prv to resume while control flow evidence is transmitted to Vrf.
arXiv Detail & Related papers (2026-03-02T18:26:17Z) - Generalizing GNNs with Tokenized Mixture of Experts [75.8310720413187]
We show that improving stability requires reducing reliance on shift-sensitive features, leaving an irreducible worst-case generalization floor.<n>We propose STEM-GNN, a pretrain-then-finetune framework with a mixture-of-experts encoder for diverse computation paths.<n>Across nine node, link, and graph benchmarks, STEM-GNN achieves a stronger three-way balance, improving robustness to degree/homophily shifts and to feature/edge corruptions while remaining competitive on clean graphs.
arXiv Detail & Related papers (2026-02-09T22:48:30Z) - Multi-Agent-Driven Cognitive Secure Communications in Satellite-Terrestrial Networks [58.70163955407538]
Malicious eavesdroppers pose a serious threat to private information via satellite-terrestrial networks (STNs)<n>We propose a cognitive secure communication framework driven by multiple agents that coordinates spectrum scheduling and protection through real-time sensing.<n>We exploit generative adversarial networks to produce adversarial matrices, and employ learning-aided power control to set real and adversarial signal powers for protection layer.
arXiv Detail & Related papers (2026-01-06T10:30:41Z) - Dual-Domain Deep Learning-Assisted NOMA-CSK Systems for Secure and Efficient Vehicular Communications [36.359307639974524]
This paper proposes a deep learning-assisted power domain non-orthogonal multiple access chaos shift keying (DL-NOMA-CSK) system for vehicular communications.<n>A deep neural network (DNN)-based demodulator is designed to learn intrinsic chaotic signal characteristics during offline training.<n>The proposed system achieves superior performance in terms of spectral efficiency (SE), energy efficiency (EE), bit error rate (BER), security, and robustness.
arXiv Detail & Related papers (2025-10-23T13:41:00Z) - ConQuER: Modular Architectures for Control and Bias Mitigation in IQP Quantum Generative Models [40.972673943861075]
Quantum generative models based on instantaneous quantum (IQP) circuits show great promise in learning complex distributions.<n>Current implementations suffer from lack of controllability over generated outputs and severe generation bias towards certain expected patterns.<n>We present a Controllable Quantum Generative Framework, ConQuER, which addresses both challenges through a modular circuit architecture.
arXiv Detail & Related papers (2025-09-26T16:32:41Z) - Lightweight Fault Detection Architecture for NTT on FPGA [0.8793721044482612]
Post-Quantum Cryptographic (PQC) algorithms are mathematically secure and resistant to quantum attacks.<n>They can still leak sensitive information in hardware implementations due to natural faults or intentional fault injections.<n>This research proposes a lightweight, efficient, recomputation-based fault detection module.
arXiv Detail & Related papers (2025-08-05T04:23:50Z) - CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus [45.24207460381396]
This paper presents a novel Intrusion Detection System (IDS) designed for the Controller Area Network (CAN) environment.<n>A RISC-V-based CAN receiver is simulated using the gem5 simulator, processing CAN frame payloads with AES-128 encryption as FreeRTOS tasks.<n>Results indicate that this approach could significantly improve CAN security and address emerging challenges in automotive cybersecurity.
arXiv Detail & Related papers (2025-07-19T20:09:52Z) - CANTXSec: A Deterministic Intrusion Detection and Prevention System for CAN Bus Monitoring ECU Activations [53.036288487863786]
We propose CANTXSec, the first deterministic Intrusion Detection and Prevention system based on physical ECU activations.<n>It detects and prevents classical attacks in the CAN bus, while detecting advanced attacks that have been less investigated in the literature.<n>We prove the effectiveness of our solution on a physical testbed, where we achieve 100% detection accuracy in both classes of attacks while preventing 100% of FIAs.
arXiv Detail & Related papers (2025-05-14T13:37:07Z) - Fooling the Decoder: An Adversarial Attack on Quantum Error Correction [49.48516314472825]
In this work, we target a basic RL surface code decoder (DeepQ) to create the first adversarial attack on quantum error correction.<n>We demonstrate an attack that reduces the logical qubit lifetime in memory experiments by up to five orders of magnitude.<n>This attack highlights the susceptibility of machine learning-based QEC and underscores the importance of further research into robust QEC methods.
arXiv Detail & Related papers (2025-04-28T10:10:05Z) - CRAFT: Characterizing and Root-Causing Fault Injection Threats at Pre-Silicon [3.6158033114580674]
Fault injection attacks pose significant security threats to embedded systems.<n>Early detection and understanding of how physical faults propagate to system-level behavior are essential to safeguarding cyberinfrastructure.<n>This work introduces CRAFT, a framework that combines pre-silicon analysis with post-silicon validation to systematically uncover and analyze fault injection vulnerabilities.
arXiv Detail & Related papers (2025-03-05T20:17:46Z) - SALTY: Explainable Artificial Intelligence Guided Structural Analysis for Hardware Trojan Detection [5.170634751744272]
Hardware Trojans are malicious modifications in digital designs that can be inserted by untrusted supply chain entities.<n>Our framework (SALTY) mitigates concerns through the use of a novel Graph Neural Network architecture.
arXiv Detail & Related papers (2025-02-19T21:40:00Z) - Unified Error Correction Code Transformer with Low Complexity [41.04310848437611]
Traditional decoders require dedicated hardware for each code, leading to high hardware costs.<n>We propose a unified Transformer-based decoder that handles multiple linear block codes within a single framework.
arXiv Detail & Related papers (2024-10-04T12:30:42Z) - SPICED: Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detection [3.048384587446267]
Many IC companies outsource manufacturing to third-party foundries, creating security risks such as stealthy analog Trojans.
Traditional detection methods, including embedding circuit watermarks or conducting hardware-based monitoring, often impose significant area and power overheads.
We propose SPICED, a framework that operates within the software domain, eliminating the need for hardware modifications for Trojan detection and localization.
arXiv Detail & Related papers (2024-08-25T17:07:08Z) - Check-Agnosia based Post-Processor for Message-Passing Decoding of Quantum LDPC Codes [3.4602940992970908]
We introduce a new post-processing algorithm with a hardware-friendly orientation, providing error correction performance competitive to the state-of-the-art techniques.
We show that latency values close to one microsecond can be obtained on the FPGA board, and provide evidence that much lower latency values can be obtained for ASIC implementations.
arXiv Detail & Related papers (2023-10-23T14:51:22Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.