Unifying Logical and Physical Layout Representations via Heterogeneous Graphs for Circuit Congestion Prediction

• URL: http://arxiv.org/abs/2603.11075v1
• Date: Tue, 10 Mar 2026 20:39:48 GMT
• Title: Unifying Logical and Physical Layout Representations via Heterogeneous Graphs for Circuit Congestion Prediction
• Abstract summary: We propose a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation.<n>Experiments on industrial benchmarks, including ISPD2015, CircuitNetN14, and CircuitNet-N28, demonstrate consistent improvements over state-of-the-art methods in prediction accuracy and correlation metrics.
• Score: 3.6554546992139385
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations. However, although prior methods incorporate both netlist connectivity and layout features, they often model the two in a loosely coupled manner and primarily produce numerical congestion estimates. We propose VeriHGN, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization. Experiments on industrial benchmarks, including ISPD2015, CircuitNet-N14, and CircuitNet-N28, demonstrate consistent improvements over state-of-the-art methods in prediction accuracy and correlation metrics.

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