An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks

• URL: http://arxiv.org/abs/2603.18054v1
• Date: Tue, 17 Mar 2026 23:39:13 GMT
• Title: An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
• Abstract summary: Spiking Neural Networks (SNNs) offer high energy efficiency and event-driven computation, ideal for low-power edge AI.<n>This paper proposes a compact System-on-Chip architecture for temporal-coding SNNs, integrating a RISC-V controller with an event-driven SNN core.<n>The architecture runs fully on a Xilinx Artix-7 FPGA, achieving up to 16x memory reduction for weights.
• Score: 0.0
• License: http://creativecommons.org/licenses/by-nc-nd/4.0/
• Abstract: Spiking Neural Networks (SNNs) offer high energy efficiency and event-driven computation, ideal for low-power edge AI. Their hardware implementation on FPGAs, however, faces challenges due to heavy computation, large memory use, and limited flexibility. This paper proposes a compact System-on-Chip (SoC) architecture for temporal-coding SNNs, integrating a RISC-V controller with an event-driven SNN core. It replaces multipliers with bitwise operations using binarized weights, includes a spike-time sorter for active spikes, and skips noninformative events to reduce computation. The architecture runs fully on a Xilinx Artix-7 FPGA, achieving up to 16x memory reduction for weights and lowering computational overhead and latency, with 97.0% accuracy on MNIST and 88.3% on FashionMNIST. This self-contained design provides an efficient, scalable platform for real-time neuromorphic inference at the edge.

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