Heuristic-Based Merging of HPC Traces to Extend Hardware Counter Coverage

• URL: http://arxiv.org/abs/2605.15832v1
• Date: Fri, 15 May 2026 10:36:15 GMT
• Title: Heuristic-Based Merging of HPC Traces to Extend Hardware Counter Coverage
• Abstract summary: We propose a methodology to merge execution traces from multiple runs, each instrumented with a different set of hardware counters.<n>Our approach matches bursts across executions by analyzing MPI structure, timing, and communication patterns.<n>The output is a new synthetic trace with all merged counters, which can be used both for HPC performance prediction and for conventional performance analysis.
• Score: 0.08399688944263843
• License: http://creativecommons.org/licenses/by-nc-sa/4.0/
• Abstract: This work extends a framework for predicting the performance of High-Performance Computing (HPC) workloads using Machine Learning (ML). A common limitation in performance modeling is the restricted number of hardware counters that can be collected simultaneously. To address this, we propose a heuristic-based methodology to merge execution traces from multiple runs, each instrumented with a different set of hardware counters. Our approach matches computation bursts across executions by analyzing MPI structure, timing, and communication patterns. This process enables the construction of a unified dataset that includes a wider set of hardware features without relying on multiplexing. The output is a new synthetic trace with all merged counters, which can be used both for HPC performance prediction and for conventional performance analysis. The methodology has been validated on MareNostrum5 machine with a range of kernels and real applications. Results show that the merged counters maintain acceptable accuracy depending on the application, and can be directly used to train ML models on a richer feature space without prior counter selection.

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