fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection Library

• URL: http://arxiv.org/abs/2406.05999v1
• Date: Mon, 10 Jun 2024 03:38:35 GMT
• Title: fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection Library
• Authors: Binglei Lou, David Boland, Philip H. W. Leong,
• Abstract summary: Machine learning ensembles combine multiple base models to produce a more accurate output. We propose a flexible computing architecture consisting of multiple partially reconfigurable regions, pblocks, which each implement anomaly detectors. Our proof-of-concept design supports three state-of-the-art anomaly detection algorithms: Loda, RS-Hash and xStream.
• Score: 1.8570740863168362
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Machine learning ensembles combine multiple base models to produce a more accurate output. They can be applied to a range of machine learning problems, including anomaly detection. In this paper, we investigate how to maximize the composability and scalability of an FPGA-based streaming ensemble anomaly detector (fSEAD). To achieve this, we propose a flexible computing architecture consisting of multiple partially reconfigurable regions, pblocks, which each implement anomaly detectors. Our proof-of-concept design supports three state-of-the-art anomaly detection algorithms: Loda, RS-Hash and xStream. Each algorithm is scalable, meaning multiple instances can be placed within a pblock to improve performance. Moreover, fSEAD is implemented using High-level synthesis (HLS), meaning further custom anomaly detectors can be supported. Pblocks are interconnected via an AXI-switch, enabling them to be composed in an arbitrary fashion before combining and merging results at run-time to create an ensemble that maximizes the use of FPGA resources and accuracy. Through utilizing reconfigurable Dynamic Function eXchange (DFX), the detector can be modified at run-time to adapt to changing environmental conditions. We compare fSEAD to an equivalent central processing unit (CPU) implementation using four standard datasets, with speed-ups ranging from $3\times$ to $8\times$.

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