SchGen: PCB Schematic Generation with Semantic-Grounded Code Representations

• URL: http://arxiv.org/abs/2605.30345v1
• Date: Thu, 28 May 2026 17:59:50 GMT
• Title: SchGen: PCB Schematic Generation with Semantic-Grounded Code Representations
• Abstract summary: This paper presents SchGen, the first large language model that generates editable PCB schematics from natural-language requests.<n>Current schematic formats are dominated by verbose, tool-specific syntax and geometry-heavy descriptions.<n>We introduce a semantically grounded code representation that encodes schematic editing primitives with relative placement and pin-name-based wiring.
• Score: 14.65619005733256
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Printed circuit board (PCB) schematic design defines nearly all electronic hardware, but it remains manual and expertise-intensive. While generative AI has advanced digital and analog IC design, PCB schematic generation from natural-language intent is largely unexplored. This paper presents SchGen, the first large language model that generates editable PCB schematics from natural-language requests. The key challenge lies in the lack of an LLM-suited representation and a large-scale dataset. Current schematic formats are dominated by verbose, tool-specific syntax and geometry-heavy descriptions, making them difficult to generate reliably. We introduce a semantically grounded code representation that encodes schematic editing primitives with relative placement and pin-name-based wiring, transforming a geometry-driven generation problem into a semantics-driven matching task amenable to LLMs. We further construct a large-scale dataset of PCB schematics paired with user prompts via a human-agent collaborative pipeline that converts open-source hardware designs into our representation. Experiments show that SchGen significantly outperforms alternative representations and even larger general-purpose LLMs on wire connectivity accuracy and functional correctness. Our results highlight the critical role of representation design in enabling generative models for complex hardware design tasks.

Related papers

• SINA: A Fully Automated Circuit Schematic Image to Netlist Generator Using Artificial Intelligence [0.0]
  We propose SINA, an open-source circuit schematic image-to-netlist generator.<n> SINA handles both IC- and PCB-level schematics and incorporates dedicated crossing-wires detection.<n>Our experiments demonstrate an overall netlist generation accuracy of 96.67%, which is 2.72x higher compared to state-of-the-art approaches.
  arXiv  Detail & Related papers  (2026-07-02T02:24:00Z)
• VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs [5.354071922171165]
  We present VeriGraphi, a framework that introduces a spec-anchored Knowledge Graph as the architectural substrate driving the RTL generation pipeline.<n>We show that VeriGraphi enables reliable hierarchical RTL generation with minimal human intervention for RISC-V.
  arXiv  Detail & Related papers  (2026-04-16T02:30:57Z)
• Plain Transformers are Surprisingly Powerful Link Predictors [57.01966734467712]
  Link prediction is a core challenge in graph machine learning, demanding models that capture rich and complex topological dependencies.<n>While Graph Neural Networks (GNNs) are the standard solution, state-of-the-art pipelines often rely on explicit structurals or memory-intensive node embeddings.<n>We present PENCIL, an encoder-only plain Transformer that replaces hand-crafted priors with attention over sampled local subgraphs.
  arXiv  Detail & Related papers  (2026-02-02T02:45:52Z)
• PCBSchemaGen: Constraint-Guided Schematic Design via LLM for Printed Circuit Boards (PCB) [4.9615245990668795]
  Printed Circuit Board (PCB) schematic design plays an essential role in all areas of electronic industries.<n>We introduce PCBGen, the first training-free framework for PCB schematic design that comprises LLM agent and Constraint synthesis.<n>Results demonstrate that PCBGen significantly improves design accuracy and computational efficiency.
  arXiv  Detail & Related papers  (2026-01-31T04:39:43Z)
• CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Prompts [0.5219568203653523]
  Large language models (LLMs) often hallucinate in granular details, violate electrical constraints, and produce non-machine-readable outputs.<n>We present CircuitLM, a novel multi-agent LLM-aided circuit design pipeline that translates user prompts into structured, visually interpretable CircuitJSON schematics.<n>This work bridges natural language input to deployable hardware designs, enabling reliable circuit prototyping by non-experts.
  arXiv  Detail & Related papers  (2026-01-08T02:18:43Z)
• Scaling LLM Speculative Decoding: Non-Autoregressive Forecasting in Large-Batch Scenarios [76.85739138203014]
  We present SpecFormer, a novel architecture that accelerates unidirectional and attention mechanisms.<n>We demonstrate that SpecFormer achieves lower training demands and reduced computational costs.
  arXiv  Detail & Related papers  (2025-11-25T14:20:08Z)
• QiMeng-CRUX: Narrowing the Gap between Natural Language and Verilog via Core Refined Understanding eXpression [48.84841760215598]
  Large language models (LLMs) have shown promising capabilities in hardware description language (HDL) generation.<n>Existing approaches often rely on free-form natural language descriptions that are often ambiguous, redundant, and unstructured.<n>We treat hardware code generation as a complex transformation from an open-ended natural language space to a domain-specific, highly constrained target space.<n>We introduce Core Refined Understanding eXpression (CRUX), a structured intermediate space that captures the essential semantics of user intent while organizing the expression for precise Verilog code generation.
  arXiv  Detail & Related papers  (2025-11-25T09:17:32Z)
• Token Communication in the Era of Large Models: An Information Bottleneck-Based Approach [55.861432910722186]
  UniToCom is a unified token communication paradigm that treats tokens as the fundamental units for both processing and wireless transmission.<n>We propose a generative information bottleneck (GenIB) principle, which facilitates the learning of tokens that preserve essential information.<n>We employ a causal Transformer-based multimodal large language model (MLLM) at the receiver to unify the processing of both discrete and continuous tokens.
  arXiv  Detail & Related papers  (2025-07-02T14:03:01Z)
• Aggregated Structural Representation with Large Language Models for Human-Centric Layout Generation [7.980497203230983]
  We propose an Aggregation Structural Representation (ASR) module that integrates graph networks with large language models (LLMs) to preserve structural information while enhancing generative capability.<n>A comprehensive evaluation on the RICO dataset demonstrates the strong performance of ASR, both quantitatively using mean Intersection over Union (mIoU) and qualitatively through a crowdsourced user study.
  arXiv  Detail & Related papers  (2025-05-26T06:17:21Z)
• HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design [24.46771930751068]
  HiVeGen is a hierarchical Verilog generation framework that decomposes generation tasks into hierarchical submodules.<n> automatic Design Space Exploration (DSE) into hierarchy-aware prompt generation, introducing weight-based retrieval to enhance code reuse.<n>Real-time human-computer interaction to lower error-correction cost, significantly improving the quality of generated designs.
  arXiv  Detail & Related papers  (2024-12-06T19:37:53Z)
• Mechanisms of Symbol Processing for In-Context Learning in Transformer Networks [78.54913566111198]
  Large Language Models (LLMs) have demonstrated impressive abilities in symbol processing through in-context learning (ICL) We seek to understand the mechanisms that can enable robust symbol processing in transformer networks. We develop a high-level language, PSL, that allows us to write symbolic programs to do complex, abstract symbol processing.
  arXiv  Detail & Related papers  (2024-10-23T01:38:10Z)
• LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation [74.7163199054881]
  Large Language Models (LLMs) have demonstrated their capability in context understanding, logic reasoning and answer generation. We present a systematic study on the application of LLMs in the EDA field. We highlight the future research direction, focusing on applying LLMs in logic synthesis, physical design, multi-modal feature extraction and alignment of circuits.
  arXiv  Detail & Related papers  (2023-12-28T15:09:14Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.