SABLE: Minimalist Instruction-Level Authenticated Encryption for Constrained Confidential Computing

• URL: http://arxiv.org/abs/2607.16771v1
• Date: Sat, 18 Jul 2026 11:12:28 GMT
• Title: SABLE: Minimalist Instruction-Level Authenticated Encryption for Constrained Confidential Computing
• Abstract summary: We present a design exploration of a RISC-V processor architecture that enables instruction-level authenticated encryption of programs.<n>SABLE is agnostic to the underlying micro-architecture, remaining compatible with the standard RISC-V tool.<n>We implement and evaluate the designs using ASCON-128a on a Xilinx Artix-7 FPGA with the open-source NEORV32 system on chip.
• Score: 3.0128599957899858
• License: http://creativecommons.org/licenses/by-nc-nd/4.0/
• Abstract: Conventional processor designs expose code and data as plaintext throughout execution, rendering them inherently vulnerable to attacks that recover intellectual property or modify security/safety checks. Instruction-level encryption (ILE) enables CPU-level decryption, execution, and optionally authentication of individual encrypted program instructions at runtime. However, existing proposals depend on specific micro-architectures, detect corrupted instructions after they have executed, rely on non-standard ciphers, or require complex analyses of program state. In this work, we introduce and present a design exploration of a RISC-V processor architecture (SABLE) that enables minimally invasive instruction-level authenticated encryption of programs. SABLE is agnostic to the underlying micro-architecture, remaining compatible with the standard RISC-V toolchain with minor changes to post-process compiled ELF binaries. We integrate a decrypt-and-verify stage at two points (the instruction-memory wrapper and the CPU frontend) and explore seven ILE micro-architectures from a single-cycle (combinational) design to six multi-cycle (sequential) variants. We implement and evaluate the designs using ASCON-128a on a Xilinx Artix-7 FPGA with the open-source NEORV32 system on chip. Relative to baseline performance, the configurations span LUT, performance, power, and energy-per-instruction overheads of 1.6-9.3$\times$, 4.1-10.0$\times$, 1.5-8.0$\times$, and 10.4-80.0$\times$, respectively, using the Dhrystone benchmarking suite. Finally, we discuss design trade-offs, highlighting area-, performance-, and energy-aware design points.

Related papers

• HORCRUX: A Complete PQC RISC-V eXtension Architecture [37.36871652478481]
  This work presents a compact RISC-V extension for Post-Quantum Cryptography (PQC) called HORCRUX.<n>HorCRUX addresses the difficult trade-off between crypto-agility, high performance, and low resource consumption in constrained environments.<n>The extension's modular structure maintains backward compatibility with standard RISC-V cores, offering a scalable solution for deploying PQC on constrained embedded systems.
  arXiv  Detail & Related papers  (2026-07-15T15:21:26Z)
• LIPPEN: A Lightweight In-Place Pointer Encryption Architecture for Pointer Integrity [3.682404448221426]
  LIPPEN is a hardware-software co-design for full-pointer encryption that provides strong pointer integrity and confidentiality with zero metadata overhead.<n>We prototype LIPPEN on FPGA using 64-bit RISC-V Rocket and BOOM cores, and evaluate it with microbenchmarks, nbench, and SPEC CPU 2017.
  arXiv  Detail & Related papers  (2026-05-05T16:58:17Z)
• Xe-Forge: Multi-Stage LLM-Powered Kernel Optimization for Intel GPU [38.81440160993858]
  Porting deep learning algorithms to new hardware accelerators requires developers to apply the same low-level optimizations to every Triton kernel in their code-base.<n>We present Xe-Forge, a multi-stage LLM-powered pipeline that automates this process for Intel GPU.<n>A curated knowledge base encodes Intel GPU constraints that are absent from LLM training data, keeping the model within architecturally valid bounds.
  arXiv  Detail & Related papers  (2026-04-16T20:21:01Z)
• CryptRISC: A Secure RISC-V Processor for High-Performance Cryptography with Power Side-Channel Protection [1.5866931449827322]
  CryptRISC is the first RISC-V processor that combines cryptographic acceleration with hardware-level power side-channel resistance.<n>Masking is a widely used countermeasure, yet software-based techniques often introduce significant performance overhead and implementation complexity.
  arXiv  Detail & Related papers  (2026-02-23T19:13:35Z)
• CryptOracle: A Modular Framework to Characterize Fully Homomorphic Encryption [3.5348336893819554]
  This paper presents a detailed characterization of OpenFHE, a comprehensive open-source library for FHE.<n>We introduce CryptOracle, a modular evaluation framework comprising (1) a benchmark suite, (2) a hardware profiler, and (3) a predictive performance model.
  arXiv  Detail & Related papers  (2025-10-03T23:30:29Z)
• Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V [0.0]
  Hardware-assisted cryptographic instructions, such as Intel's AES-NI and ARM's custom instructions for encryption workloads, have demonstrated substantial performance improvements.<n>However, efficient SHA-3 acceleration remains an open problem due to its distinct permutation-based structure and memory access patterns.<n>This study investigates the architectural challenges of embedding a SHA-3 permutation operation as a custom instruction within a general-purpose processor.
  arXiv  Detail & Related papers  (2025-08-28T10:57:13Z)
• ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols [45.66401695351214]
  We introduce ProtocolLLM, the first benchmark suite specifically targeting widely used SystemVerilog protocols.<n>We observe that most of the models fail to generate SystemVerilog code for communication protocols that follow timing constrains.
  arXiv  Detail & Related papers  (2025-06-09T17:10:47Z)
• Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis [45.471039079664656]
  Domain-specific accelerators (DSAs) have gained popularity for applications such as deep learning and autonomous driving. We propose ProgSG, a model that allows interaction between the source code sequence modality and the graph modality in a deep and fine-grained way. We show that ProgSG reduces the RMSE of design performance predictions by up to $22%$, and identifies designs with an average of $1.10times$.
  arXiv  Detail & Related papers  (2024-06-13T22:34:58Z)
• A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation [40.8381466360025]
  nano-UAVs face significant power and payload constraints while requiring advanced computing capabilities. We present Shaheen, a 9mm2 200mW system-on-a-chip (SoC) It integrates a Linux-capable RV64 core, compliant with the v1.0 ratified Hypervisor extension, along with a low-cost and low-power memory controller. At the same time, it integrates a fully programmable energy- and area-efficient multi-core cluster of RV32 cores optimized for general-purpose DSP.
  arXiv  Detail & Related papers  (2024-01-07T16:03:47Z)
• SOCI^+: An Enhanced Toolkit for Secure OutsourcedComputation on Integers [50.608828039206365]
  We propose SOCI+ which significantly improves the performance of SOCI. SOCI+ employs a novel (2, 2)-threshold Paillier cryptosystem with fast encryption and decryption as its cryptographic primitive. Compared with SOCI, our experimental evaluation shows that SOCI+ is up to 5.4 times more efficient in computation and 40% less in communication overhead.
  arXiv  Detail & Related papers  (2023-09-27T05:19:32Z)
• Citadel: Simple Spectre-Safe Isolation For Real-World Programs That Share Memory [8.414722884952525]
  We introduce a new security property we call relaxed microarchitectural isolation (RMI)<n>RMI allows sensitive programs that are not-constant-time to share memory with an attacker while restricting the information leakage to that of non-speculative execution.<n>Our end-to-end prototype, Citadel, consists of an FPGA-based multicore processor that boots Linux and runs secure applications.
  arXiv  Detail & Related papers  (2023-06-26T17:51:23Z)
• ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation [38.023395256208055]
  High-level synthesis (HLS) allows a developer to compile a high-level description in the form of software code in C and C++. HLS tools still require microarchitecture decisions, expressed in terms of pragmas. We propose ProgSG allowing the source code sequence modality and the graph modalities to interact with each other in a deep and fine-grained way.
  arXiv  Detail & Related papers  (2023-05-18T09:44:18Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.