End-to-End Memristive HTM System for Pattern Recognition and Sequence Prediction

• URL: http://arxiv.org/abs/2006.11958v1
• Date: Mon, 22 Jun 2020 01:12:14 GMT
• Title: End-to-End Memristive HTM System for Pattern Recognition and Sequence Prediction
• Authors: Abdullah M. Zyarah, Kevin Gomez, and Dhireesha Kudithipudi
• Abstract summary: A neuromorphic system that processes-temporal information on the edge is proposed. The proposed architecture is benchmarked to predict on real-world streaming data. System offers 3.46X reduction in latency and 77.02X reduction in power consumption.
• Score: 4.932130498861988
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Neuromorphic systems that learn and predict from streaming inputs hold significant promise in pervasive edge computing and its applications. In this paper, a neuromorphic system that processes spatio-temporal information on the edge is proposed. Algorithmically, the system is based on hierarchical temporal memory that inherently offers online learning, resiliency, and fault tolerance. Architecturally, it is a full custom mixed-signal design with an underlying digital communication scheme and analog computational modules. Therefore, the proposed system features reconfigurability, real-time processing, low power consumption, and low-latency processing. The proposed architecture is benchmarked to predict on real-world streaming data. The network's mean absolute percentage error on the mixed-signal system is 1.129X lower compared to its baseline algorithm model. This reduction can be attributed to device non-idealities and probabilistic formation of synaptic connections. We demonstrate that the combined effect of Hebbian learning and network sparsity also plays a major role in extending the overall network lifespan. We also illustrate that the system offers 3.46X reduction in latency and 77.02X reduction in power consumption when compared to a custom CMOS digital design implemented at the same technology node. By employing specific low power techniques, such as clock gating, we observe 161.37X reduction in power consumption.

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