Implementation of a Binary Neural Network on a Passive Array of Magnetic
Tunnel Junctions
- URL: http://arxiv.org/abs/2112.09159v1
- Date: Thu, 16 Dec 2021 19:11:29 GMT
- Title: Implementation of a Binary Neural Network on a Passive Array of Magnetic
Tunnel Junctions
- Authors: Jonathan M. Goodwill, Nitin Prasad, Brian D. Hoskins, Matthew W.
Daniels, Advait Madhavan, Lei Wan, Tiffany S. Santos, Michael Tran, Jordan A.
Katine, Patrick M. Braganca, Mark D. Stiles, and Jabez J. McClelland
- Abstract summary: We leverage the low-power and the inherently binary operation of magnetic tunnel junctions (MTJs) to demonstrate neural network hardware inference based on passive arrays of MTJs.
We achieve software-equivalent accuracy of up to 95.3 % with proper tuning of network parameters in 15 x 15 MTJ arrays having a range of device sizes.
- Score: 2.917306244908168
- License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
- Abstract: The increasing scale of neural networks and their growing application space
have produced demand for more energy- and memory-efficient
artificial-intelligence-specific hardware. Avenues to mitigate the main issue,
the von Neumann bottleneck, include in-memory and near-memory architectures, as
well as algorithmic approaches. Here we leverage the low-power and the
inherently binary operation of magnetic tunnel junctions (MTJs) to demonstrate
neural network hardware inference based on passive arrays of MTJs. In general,
transferring a trained network model to hardware for inference is confronted by
degradation in performance due to device-to-device variations, write errors,
parasitic resistance, and nonidealities in the substrate. To quantify the
effect of these hardware realities, we benchmark 300 unique weight matrix
solutions of a 2-layer perceptron to classify the Wine dataset for both
classification accuracy and write fidelity. Despite device imperfections, we
achieve software-equivalent accuracy of up to 95.3 % with proper tuning of
network parameters in 15 x 15 MTJ arrays having a range of device sizes. The
success of this tuning process shows that new metrics are needed to
characterize the performance and quality of networks reproduced in mixed signal
hardware.
Related papers
- Neuromorphic Wireless Split Computing with Multi-Level Spikes [69.73249913506042]
In neuromorphic computing, spiking neural networks (SNNs) perform inference tasks, offering significant efficiency gains for workloads involving sequential data.
Recent advances in hardware and software have demonstrated that embedding a few bits of payload in each spike exchanged between the spiking neurons can further enhance inference accuracy.
This paper investigates a wireless neuromorphic split computing architecture employing multi-level SNNs.
arXiv Detail & Related papers (2024-11-07T14:08:35Z) - TrIM: Triangular Input Movement Systolic Array for Convolutional Neural Networks -- Part II: Architecture and Hardware Implementation [0.0]
TrIM is an innovative dataflow based on a triangular movement of inputs.
TrIM can reduce the number of memory accesses by one order of magnitude when compared to state-of-the-art systolic arrays.
architecture achieves a peak throughput of 453.6 Giga Operations per Second.
arXiv Detail & Related papers (2024-08-05T10:18:00Z) - Efficient and accurate neural field reconstruction using resistive memory [52.68088466453264]
Traditional signal reconstruction methods on digital computers face both software and hardware challenges.
We propose a systematic approach with software-hardware co-optimizations for signal reconstruction from sparse inputs.
This work advances the AI-driven signal restoration technology and paves the way for future efficient and robust medical AI and 3D vision applications.
arXiv Detail & Related papers (2024-04-15T09:33:09Z) - Measurement-driven neural-network training for integrated magnetic tunnel junction arrays [0.9682994745050424]
We show that even a small number of defects in physically mapped networks significantly degrades the performance of networks trained without defects.
We then demonstrate a robust training method that extends hardware-aware training to statistics-aware training.
arXiv Detail & Related papers (2023-12-11T15:28:47Z) - Quantization of Deep Neural Networks to facilitate self-correction of
weights on Phase Change Memory-based analog hardware [0.0]
We develop an algorithm to approximate a set of multiplicative weights.
These weights aim to represent the original network's weights with minimal loss in performance.
Our results demonstrate that, when paired with an on-chip pulse generator, our self-correcting neural network performs comparably to those trained with analog-aware algorithms.
arXiv Detail & Related papers (2023-09-30T10:47:25Z) - Synaptic metaplasticity with multi-level memristive devices [1.5598974049838272]
We propose a memristor-based hardware solution for implementing metaplasticity during both inference and training.
We show that a two-layer perceptron achieves 97% and 86% accuracy on consecutive training of MNIST and Fashion-MNIST.
Our architecture is compatible with the memristor limited endurance and has a 15x reduction in memory.
arXiv Detail & Related papers (2023-06-21T09:40:25Z) - Signal Detection in MIMO Systems with Hardware Imperfections: Message
Passing on Neural Networks [101.59367762974371]
In this paper, we investigate signal detection in multiple-input-multiple-output (MIMO) communication systems with hardware impairments.
It is difficult to train a deep neural network (DNN) with limited pilot signals, hindering its practical applications.
We design an efficient message passing based Bayesian signal detector, leveraging the unitary approximate message passing (UAMP) algorithm.
arXiv Detail & Related papers (2022-10-08T04:32:58Z) - DS-Net++: Dynamic Weight Slicing for Efficient Inference in CNNs and
Transformers [105.74546828182834]
We show a hardware-efficient dynamic inference regime, named dynamic weight slicing, which adaptively slice a part of network parameters for inputs with diverse difficulty levels.
We present dynamic slimmable network (DS-Net) and dynamic slice-able network (DS-Net++) by input-dependently adjusting filter numbers of CNNs and multiple dimensions in both CNNs and transformers.
arXiv Detail & Related papers (2021-09-21T09:57:21Z) - Quantized Neural Networks via {-1, +1} Encoding Decomposition and
Acceleration [83.84684675841167]
We propose a novel encoding scheme using -1, +1 to decompose quantized neural networks (QNNs) into multi-branch binary networks.
We validate the effectiveness of our method on large-scale image classification, object detection, and semantic segmentation tasks.
arXiv Detail & Related papers (2021-06-18T03:11:15Z) - Lightweight Residual Densely Connected Convolutional Neural Network [18.310331378001397]
The lightweight residual densely connected blocks are proposed to guaranty the deep supervision, efficient gradient flow, and feature reuse abilities of convolutional neural network.
The proposed method decreases the cost of training and inference processes without using any special hardware-software equipment.
arXiv Detail & Related papers (2020-01-02T17:15:32Z) - PatDNN: Achieving Real-Time DNN Execution on Mobile Devices with
Pattern-based Weight Pruning [57.20262984116752]
We introduce a new dimension, fine-grained pruning patterns inside the coarse-grained structures, revealing a previously unknown point in design space.
With the higher accuracy enabled by fine-grained pruning patterns, the unique insight is to use the compiler to re-gain and guarantee high hardware efficiency.
arXiv Detail & Related papers (2020-01-01T04:52:07Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.