Optimization of Quantum Read-Only Memory Circuits

• URL: http://arxiv.org/abs/2204.03097v1
• Date: Wed, 6 Apr 2022 21:23:31 GMT
• Title: Optimization of Quantum Read-Only Memory Circuits
• Authors: Koustubh Phalak, Mahabubul Alam, Abdullah Ash-Saki, Rasit Onur Topaloglu and Swaroop Ghosh
• Abstract summary: In quantum machine learning applications, a quantum memory can simplify the data loading process and potentially accelerate the learning task. Quantum Read Only Memory (QROM) scale exponentially with the number of address lines making them impractical in state-of-the-art Noisy Intermediate-Scale Quantum (NISQ) computers beyond 4-bit addresses. We propose techniques such as, predecoding logic and qubit reset to reduce the depth and gate count of QROM circuits to target wider address ranges such as, 8-bits.
• Score: 5.486046841722322
• License: http://creativecommons.org/licenses/by-nc-nd/4.0/
• Abstract: Quantum computing is a rapidly expanding field with applications ranging from optimization all the way to complex machine learning tasks. Quantum memories, while lacking in practical quantum computers, have the potential to bring quantum advantage. In quantum machine learning applications for example, a quantum memory can simplify the data loading process and potentially accelerate the learning task. Quantum memory can also store intermediate quantum state of qubits that can be reused for computation. However, the depth, gate count and compilation time of quantum memories such as, Quantum Read Only Memory (QROM) scale exponentially with the number of address lines making them impractical in state-of-the-art Noisy Intermediate-Scale Quantum (NISQ) computers beyond 4-bit addresses. In this paper, we propose techniques such as, predecoding logic and qubit reset to reduce the depth and gate count of QROM circuits to target wider address ranges such as, 8-bits. The proposed approach reduces the number of gates and depth count by at least 2X compared to the naive implementation at only 36% qubit overhead. A reduction in circuit depth and gate count as high as 75X and compilation time by 85X at the cost of a maximum of 2.28X qubit overhead is observed. Experimentally, the fidelity with the proposed predecoding circuit compared to existing optimization approach is also higher (as much as 73% compared to 40.8%) under reduced error rates.

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