Better Than Worst-Case Decoding for Quantum Error Correction

• URL: http://arxiv.org/abs/2208.08547v2
• Date: Tue, 25 Oct 2022 05:17:42 GMT
• Title: Better Than Worst-Case Decoding for Quantum Error Correction
• Authors: Gokul Subramanian Ravi, Jonathan M. Baker, Arash Fayyazi, Sophia Fuhui Lin, Ali Javadi-Abhari, Massoud Pedram and Frederic T. Chong
• Abstract summary: We propose a lightweight decoder for decoding and correcting trivial common-case errors on superconducting quantum systems. The decoder is implemented for SFQ logic. It achieves 10-10000x bandwidth reduction over prior off-chip bandwidth reduction techniques. It achieves a 15-37x resource overhead reduction compared to prior on-chip-only decoding.
• Score: 6.943255454097062
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: The overheads of classical decoding for quantum error correction on superconducting quantum systems grow rapidly with the number of logical qubits and their correction code distance. Decoding at room temperature is bottle-necked by refrigerator I/O bandwidth while cryogenic on-chip decoding is limited by area/power/thermal budget. To overcome these overheads, we are motivated by the observation that in the common case, error signatures are fairly trivial with high redundancy/sparsity, since the error correction codes are over-provisioned to correct for uncommon worst-case complex scenarios (to ensure substantially low logical error rates). If suitably exploited, these trivial signatures can be decoded and corrected with insignificant overhead, thereby alleviating the bottlenecks described above, while still handling the worst-case complex signatures by state-of-the-art means. Our proposal, targeting Surface Codes, consists of: 1) Clique: A lightweight decoder for decoding and correcting trivial common-case errors, designed for the cryogenic domain. The decoder is implemented for SFQ logic. 2) A statistical confidence-based technique for off-chip decoding bandwidth allocation, to efficiently handle rare complex decodes which are not covered by the on-chip decoder. 3) A method for stalling circuit execution, for the worst-case scenarios in which the provisioned off-chip bandwidth is insufficient to complete all requested off-chip decodes. In all, our proposal enables 70-99+% off-chip bandwidth elimination across a range of logical and physical error rates, without significantly sacrificing the accuracy of state-of-the-art off-chip decoding. By doing so, it achieves 10-10000x bandwidth reduction over prior off-chip bandwidth reduction techniques. Furthermore, it achieves a 15-37x resource overhead reduction compared to prior on-chip-only decoding.

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