Wafer Map Defect Patterns Semi-Supervised Classification Using Latent Vector Representation

• URL: http://arxiv.org/abs/2311.12840v1
• Date: Fri, 6 Oct 2023 08:23:36 GMT
• Title: Wafer Map Defect Patterns Semi-Supervised Classification Using Latent Vector Representation
• Authors: Qiyu Wei and Wei Zhao and Xiaoyan Zheng and Zeng Zeng
• Abstract summary: The demand for defect detection during integrated circuit fabrication stages is becoming increasingly critical. Traditional wafer map defect pattern detection methods involve manual inspection using electron microscopes. We propose a model capable of automatically detecting defects as an alternative to manual operations.
• Score: 8.400553138721044
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: As the globalization of semiconductor design and manufacturing processes continues, the demand for defect detection during integrated circuit fabrication stages is becoming increasingly critical, playing a significant role in enhancing the yield of semiconductor products. Traditional wafer map defect pattern detection methods involve manual inspection using electron microscopes to collect sample images, which are then assessed by experts for defects. This approach is labor-intensive and inefficient. Consequently, there is a pressing need to develop a model capable of automatically detecting defects as an alternative to manual operations. In this paper, we propose a method that initially employs a pre-trained VAE model to obtain the fault distribution information of the wafer map. This information serves as guidance, combined with the original image set for semi-supervised model training. During the semi-supervised training, we utilize a teacher-student network for iterative learning. The model presented in this paper is validated on the benchmark dataset WM-811K wafer dataset. The experimental results demonstrate superior classification accuracy and detection performance compared to state-of-the-art models, fulfilling the requirements for industrial applications. Compared to the original architecture, we have achieved significant performance improvement.

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