Ab initio modelling of quantum dot qubits: Coupling, gate dynamics and
robustness versus charge noise
- URL: http://arxiv.org/abs/2403.00191v1
- Date: Thu, 29 Feb 2024 23:43:22 GMT
- Title: Ab initio modelling of quantum dot qubits: Coupling, gate dynamics and
robustness versus charge noise
- Authors: Hamza Jnane, Simon C Benjamin
- Abstract summary: Commercial semiconductor foundries can create quantum processors (QPs) using the same processes employed for conventional chips.
To identify the most promising options for fabrication, one requires predictive modeling of interacting electrons in real geometries.
In this work we explore a modelling method based on real-space grids, an ab initio approach without assumptions relating to device topology.
- Score: 0.0
- License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
- Abstract: Electron spins in semiconductor devices are highly promising building blocks
for quantum processors (QPs). Commercial semiconductor foundries can create QPs
using the same processes employed for conventional chips, once the QP design is
suitably specified. There is a vast accessible design space; to identify the
most promising options for fabrication, one requires predictive modeling of
interacting electrons in real geometries and complex non-ideal environments. In
this work we explore a modelling method based on real-space grids, an ab initio
approach without assumptions relating to device topology and therefore with
wide applicability. Given an electrode geometry, we determine the exchange
coupling between quantum dot qubits, and model the full evolution of a
$\sqrt{\text{SWAP}}$ gate to predict qubit loss and infidelity rates for
various voltage profiles. Moreover we explore the impact of unwanted charge
defects (static and dynamic) in the environment, and test robust pulse
sequences. As an example we exhibit a sequence correcting both systematic
errors and (unknown) charge defects, observing an order of magnitude boost in
fidelity. The technique can thus identify the most promising device designs for
fabrication, as well as bespoke control sequences for each such device.
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