Related papers: Wafer-scale uniformity improvement of Dolan-bridge Josephson junction by shadow evaporation bias correction

Wafer-scale uniformity improvement of Dolan-bridge Josephson junction by shadow evaporation bias correction

URL: http://arxiv.org/abs/2403.01894v2
Date: Mon, 15 Apr 2024 09:02:51 GMT
Title: Wafer-scale uniformity improvement of Dolan-bridge Josephson junction by shadow evaporation bias correction
Authors: Daria A. Moskaleva, Nikita D. Korshakov, Dmitry O. Moskalev, Anastasiya A. Solovyova, Alexey R. Matanin, Elizaveta I. Malevannaya, Nikita S. Smirnov, Maksim I. Teleganov, Yuri V. Panfilov, Ilya A. Rodionov,
Abstract summary: We report on a robust wafer-scale Al/AlOx/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias mask correction and comprehensive oxidation optimization. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.
Score: 0.0
License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
Abstract: One of the practical limitations of solid-state superconducting quantum processors technology is frequency crowding due to low qubits fabrication reproducibility. Josephson junction 100 nm-scale nonlinear inductance of the qubits still suffers from Dolan-bridge shadow evaporation process. Here, we report on a robust wafer-scale Al/AlOx/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias resist mask correction and comprehensive oxidation optimization. We introduce topology correction model for two-layer resist mask biasing at a wafer-scale, which takes into account an evaporation source geometry. It results in Josephson junction area variation coefficient improvement down to 1.1% for the critical dimensions from 130x170 nm2 to 130x670 nm2 over 70x70 mm2 (49 cm2) wafer working area. Next, we investigate JJ oxidation process (oxidation method, pressure and time) and its impact on a room temperature resistance reproducibility. Finally, we combine both shadow evaporation bias correction and oxidation best practices for 4-inch wafers improving room temperature resistance variation coefficient down to 6.0/5.2/4.1% for 0.025 {\mu}m2 JJ area and 4.0/3.4/2.3% for 0.090 {\mu}m2 JJ area for 49/25/16 cm2 wafer working area correspondingly. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.

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