Parallel and real-time post-processing for quantum random number generators

• URL: http://arxiv.org/abs/2403.19479v1
• Date: Thu, 28 Mar 2024 15:05:39 GMT
• Title: Parallel and real-time post-processing for quantum random number generators
• Authors: Xiaomin Guo, Fading Lin, Jiehong Lin, Zhijie Song, Yue luo, Qiqi Wang, Yanqiang Guo,
• Abstract summary: This work explores the parallel and real-time implementation of multiple seed real-time updating toeplitz hash extractors in an FPGA to achieve parallel QRNGs. With the use of higher-performance ADCs, we attained a random number production rate exceeding 20Gbps. This marks a significant step toward chip-based parallel QRNGs, enhancing the practicality of CV QRNGs in trusted, device-independent, and semi-device-independent scenarios.
• Score: 5.864108266054829
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Quantum systems are particularly suited for generating true randomness due to their inherent unpredictability, which can be justified on physical principles. However, practical implementations of Quantum RNGs (QRNGs) are always subject to noise, or uncontrollable influences, diminishing the quality of raw randomness produced. This necessitates post-processing to convert raw output into genuine randomness. In current QRNG implementations, the critical issue of seed updating is often overlooked, risking security vulnerabilities due to increased security parameters when seeds are reused in post-processing, and frequent seed updates fail to yield net randomness, while reusing seeds relies on the assumption that the original sequence inputs are independent.In this work, we have provided a specific scheme for seed updates that balances practicality and security, exploring the parallel and real-time implementation of multiple seed real-time updating toeplitz hash extractors in an FPGA to achieve parallel QRNGs, focusing on efficient hardware computation resource use. Through logic optimization, we achieved a greater number of parallel channels and a post-processing matrix size three times larger than previous works on the same FPGA platform, utilizing fewer logic resources. This resulted in a higher rate of random number generation and enhanced security. Furthermore, with the use of higher-performance ADCs, we attained a random number production rate exceeding 20Gbps.High-speed random number transfer and seed updating were achieved using the PCIe high-speed interface.This marks a significant step toward chip-based parallel QRNGs, enhancing the practicality of CV QRNGs in trusted, device-independent, and semi-device-independent scenarios.

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