LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation

• URL: http://arxiv.org/abs/2406.05250v2
• Date: Wed, 19 Jun 2024 20:49:26 GMT
• Title: LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation
• Authors: Guojin Chen, Keren Zhu, Seunggeun Kim, Hanqing Zhu, Yao Lai, Bei Yu, David Z. Pan,
• Abstract summary: This paper presents the textttLLANA framework for analog layout synthesis. It exploits the few-shot learning abilities of Large Language Models (LLMs) for more efficient generation of analog design-dependent parameter constraints. Results demonstrate that textttLLANA not only achieves performance comparable to state-of-the-art (SOTA) BO methods but also enables a more effective exploration of the analog circuit design space.
• Score: 13.860831058885314
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Analog layout synthesis faces significant challenges due to its dependence on manual processes, considerable time requirements, and performance instability. Current Bayesian Optimization (BO)-based techniques for analog layout synthesis, despite their potential for automation, suffer from slow convergence and extensive data needs, limiting their practical application. This paper presents the \texttt{LLANA} framework, a novel approach that leverages Large Language Models (LLMs) to enhance BO by exploiting the few-shot learning abilities of LLMs for more efficient generation of analog design-dependent parameter constraints. Experimental results demonstrate that \texttt{LLANA} not only achieves performance comparable to state-of-the-art (SOTA) BO methods but also enables a more effective exploration of the analog circuit design space, thanks to LLM's superior contextual understanding and learning efficiency. The code is available at https://github.com/dekura/LLANA.

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