Fault-tolerant resource estimation using graph-state compilation on a modular superconducting architecture

• URL: http://arxiv.org/abs/2406.06015v1
• Date: Mon, 10 Jun 2024 04:30:48 GMT
• Title: Fault-tolerant resource estimation using graph-state compilation on a modular superconducting architecture
• Authors: S. N. Saadatmand, Tyler L. Wilson, Mark Field, Madhav Krishnan Vijayan, Thinh P. Le, Jannis Ruh, Arshpreet Singh Maan, Ioana Moflic, Athena Caesura, Alexandru Paler, Mark J. Hodson, Simon J. Devitt, Josh Y. Mutus,
• Abstract summary: Development of fault-tolerant quantum computers (FTQCs) is gaining increased attention within the quantum computing community. We present a resource estimation framework and software tool that estimates the physical resources required to execute specific quantum algorithms. This tool can predict the size, power consumption, and execution time of these algorithms at as they approach utility-scale.
• Score: 30.01663013636363
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: The development of fault-tolerant quantum computers (FTQCs) is gaining increased attention within the quantum computing community. Like their digital counterparts, FTQCs, equipped with error correction and large qubit numbers, promise to solve some of humanity's grand challenges. Estimates of the resource requirements for future FTQC systems are essential to making design choices and prioritizing R&D efforts to develop critical technologies. Here, we present a resource estimation framework and software tool that estimates the physical resources required to execute specific quantum algorithms, compiled into their graph-state form, and laid out onto a modular superconducting hardware architecture. This tool can predict the size, power consumption, and execution time of these algorithms at as they approach utility-scale according to explicit assumptions about the system's physical layout, thermal load, and modular connectivity. We use this tool to study the total resources on a proposed modular architecture and the impact of tradeoffs between and inter-module connectivity, latency and resource requirements.

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