Optimising Iteration Scheduling for Full-State Vector Simulation of Quantum Circuits on FPGAs

• URL: http://arxiv.org/abs/2411.18354v1
• Date: Wed, 27 Nov 2024 13:57:29 GMT
• Title: Optimising Iteration Scheduling for Full-State Vector Simulation of Quantum Circuits on FPGAs
• Authors: Youssef Moawad, Andrew Brown, René Steijl, Wim Vanderbauwhede,
• Abstract summary: We present a memory access pattern to optimise the number of iterations that need to be scheduled to execute a quantum gate. We show that this approach results in a significant reduction in the time required to simulate a gate for each added control qubit.
• Score: 1.221089353510972
• License:
• Abstract: As the field of quantum computing grows, novel algorithms which take advantage of quantum phenomena need to be developed. As we are currently in the NISQ (noisy intermediate scale quantum) era, quantum algorithm researchers cannot reliably test their algorithms on real quantum hardware, which is still too limited. Instead, quantum computing simulators on classical computing systems are used. In the quantum circuit model, quantum bits (qubits) are operated on by quantum gates. A quantum circuit is a sequence of such quantum gates operating on some number of qubits. A quantum gate applied to a qubit can be controlled by other qubits in the circuit. This applies the gate only to the states which satisfy the required control qubit state. We particularly target FPGAs as our main simulation platform, as these offer potential energy savings when compared to running simulations on CPUs/GPUs. In this work, we present a memory access pattern to optimise the number of iterations that need to be scheduled to execute a quantum gate such that only the iterations which access the required pairs (determined according to the control qubits imposed on the gate) are scheduled. We show that this approach results in a significant reduction in the time required to simulate a gate for each added control qubit. We also show that this approach benefits the simulation time on FPGAs more than CPUs and GPUs and allows to outperform both CPU and GPU platforms in terms of energy efficiency, which is the main factor for scalability of the simulations.

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