Hardware-Efficient Photonic Tensor Core: Accelerating Deep Neural Networks with Structured Compression

• URL: http://arxiv.org/abs/2502.01670v2
• Date: Wed, 23 Jul 2025 07:39:55 GMT
• Title: Hardware-Efficient Photonic Tensor Core: Accelerating Deep Neural Networks with Structured Compression
• Authors: Shupeng Ning, Hanqing Zhu, Chenghao Feng, Jiaqi Gu, David Z. Pan, Ray T. Chen,
• Abstract summary: We introduce a block-circulant photonic tensor core for a structure-compressed optical neural network (StrC-ONN) architecture.<n>This work explores a new pathway toward practical and scalable ONNs, highlighting a promising route to address future computational efficiency challenges.
• Score: 15.665630650382226
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: The rapid growth in computing demands, particularly driven by artificial intelligence applications, has begun to exceed the capabilities of traditional electronic hardware. Optical computing offers a promising alternative due to its parallelism, high computational speed, and low power consumption. However, existing photonic integrated circuits are constrained by large footprints, costly electro-optical interfaces, and complex control mechanisms, limiting the practical scalability of optical neural networks (ONNs). To address these limitations, we introduce a block-circulant photonic tensor core for a structure-compressed optical neural network (StrC-ONN) architecture. The structured compression technique substantially reduces both model complexity and hardware resources without sacrificing the versatility of neural networks, and achieves accuracy comparable to uncompressed models. Additionally, we propose a hardware-aware training framework to compensate for on-chip nonidealities to improve model robustness and accuracy. Experimental validation through image processing and classification tasks demonstrates that our StrC-ONN achieves a reduction in trainable parameters of up to 74.91%,while still maintaining competitive accuracy levels. Performance analyses further indicate that this hardware-software co-design approach is expected to yield a 3.56 times improvement in power efficiency. By reducing both hardware requirements and control complexity across multiple dimensions, this work explores a new pathway toward practical and scalable ONNs, highlighting a promising route to address future computational efficiency challenges.

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