Reinforcement learning framework for the mechanical design of microelectronic components under multiphysics constraints

• URL: http://arxiv.org/abs/2504.17142v1
• Date: Wed, 23 Apr 2025 23:20:44 GMT
• Title: Reinforcement learning framework for the mechanical design of microelectronic components under multiphysics constraints
• Authors: Siddharth Nair, Timothy F. Walsh, Greg Pickrell, Fabio Semperlotti,
• Abstract summary: This study focuses on the development of reinforcement learning based techniques for the design of microelectronic components under multiphysics constraints.<n>By taking as prototypical elements an application-specific integrated circuit (ASIC) and a heterogeneously integrated (HI) interposer, we develop and numerically test an optimization framework based on reinforcement learning (RL)<n>More specifically, we consider the optimization of the bonded interconnect geometry for an ASIC chip as well as the placement of components on a HI interposer while satisfying thermoelastic and design constraints.
• Score: 0.0
• License: http://creativecommons.org/licenses/by-nc-sa/4.0/
• Abstract: This study focuses on the development of reinforcement learning based techniques for the design of microelectronic components under multiphysics constraints. While traditional design approaches based on global optimization approaches are effective when dealing with a small number of design parameters, as the complexity of the solution space and of the constraints increases different techniques are needed. This is an important reason that makes the design and optimization of microelectronic components (characterized by large solution space and multiphysics constraints) very challenging for traditional methods. By taking as prototypical elements an application-specific integrated circuit (ASIC) and a heterogeneously integrated (HI) interposer, we develop and numerically test an optimization framework based on reinforcement learning (RL). More specifically, we consider the optimization of the bonded interconnect geometry for an ASIC chip as well as the placement of components on a HI interposer while satisfying thermoelastic and design constraints. This placement problem is particularly interesting because it features a high-dimensional solution space.

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