CMOS-Compatible, Wafer-Scale Processed Superconducting Qubits Exceeding Energy Relaxation Times of 200us

• URL: http://arxiv.org/abs/2505.08424v3
• Date: Tue, 20 May 2025 12:35:47 GMT
• Title: CMOS-Compatible, Wafer-Scale Processed Superconducting Qubits Exceeding Energy Relaxation Times of 200us
• Authors: T. Mayer, J. Weber, E. Music, C. Moran Guizan, S. J. K. Lang, L. Schwarzenbach, C. Dhieb, B. Kiliclar, A. Maiwald, Z. Luo, W. Lerch, D. Zahn, I. Eisele, R. N. Pereira, C. Kutter,
• Abstract summary: We present the results of an industry-grade fabrication of superconducting qubits on 200 mm wafers.<n>We demonstrate a Josephson junction fabrication yield of 99.7% (shorts and opens) across more than 10000 junctions and a qubit frequency prediction accuracy of 1.6%.<n>This represents the best performance reported so far for superconducting qubits fabricated by industry-grade, wafer-level subtractive processes.
• Score: 0.0
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: We present the results of an industry-grade fabrication of superconducting qubits on 200 mm wafers utilizing CMOS-established processing methods. By automated waferprober resistance measurements at room temperature, we demonstrate a Josephson junction fabrication yield of 99.7% (shorts and opens) across more than 10000 junctions and a qubit frequency prediction accuracy of 1.6%. In cryogenic characterization, we provide statistical results regarding energy relaxation times of the qubits with a median T1 of up to 100 us and individual devices consistently approaching 200 us in long-term measurements. This represents the best performance reported so far for superconducting qubits fabricated by industry-grade, wafer-level subtractive processes.

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