Distributed Realization of Color Codes for Quantum Error Correction

• URL: http://arxiv.org/abs/2505.10693v1
• Date: Thu, 15 May 2025 20:33:00 GMT
• Title: Distributed Realization of Color Codes for Quantum Error Correction
• Authors: Nitish Kumar Chandra, David Tipper, Reza Nejabati, Eneet Kaur, Kaushik P. Seshadreesan,
• Abstract summary: We propose and analyze a distributed architecture for realizing the (6.6.6) color code.<n>The architecture involves interconnecting patches of the color code housed in different quantum processing units (QPUs) via entangled pairs.
• Score: 0.9550226415527892
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Color codes are a leading class of topological quantum error-correcting codes with modest error thresholds and structural compatibility with two-dimensional architectures, which make them well-suited for fault-tolerant quantum computing (FTQC). Here, we propose and analyze a distributed architecture for realizing the (6.6.6) color code. The architecture involves interconnecting patches of the color code housed in different quantum processing units (QPUs) via entangled pairs. To account for noisy interconnects, we model the qubits in the color code as being subject to a bit-flip noise channel, where the qubits on the boundary (seam) between patches experience elevated noise compared to those in the bulk. We investigate the error threshold of the distributed color code under such asymmetric noise conditions by employing two decoders: a tensor-network-based decoder and a recently introduced concatenated Minimum Weight Perfect Matching (MWPM) algorithm. Our simulations demonstrate that elevated noise on seam qubits leads to a slight reduction in threshold for the tensor-network decoder, whereas the concatenated MWPM decoder shows no significant change in the error threshold, underscoring its effectiveness under asymmetric noise conditions. Our findings thus highlight the robustness of color codes in distributed architectures and provide valuable insights into the practical realization of FTQC involving noisy interconnects between QPUs.

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