VeriLocc: End-to-End Cross-Architecture Register Allocation via LLM

• URL: http://arxiv.org/abs/2506.17506v1
• Date: Fri, 20 Jun 2025 23:08:09 GMT
• Title: VeriLocc: End-to-End Cross-Architecture Register Allocation via LLM
• Abstract summary: We introduce VeriLocc, a framework that combines large language models (LLMs) with formal compiler techniques to enable generalizable and verifiable register allocation across GPU architectures.<n> evaluated on matrix multiplication (M) and multi-head attention (MHA), VeriLocc achieves 85-99% single-shot accuracy and near-100% pass@100.<n>Case study shows that VeriLocc discovers more performant assignments than expert-tuned libraries, outperforming rocBLAS by over 10% in runtime.
• Score: 39.27052626057448
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Modern GPUs evolve rapidly, yet production compilers still rely on hand-crafted register allocation heuristics that require substantial re-tuning for each hardware generation. We introduce VeriLocc, a framework that combines large language models (LLMs) with formal compiler techniques to enable generalizable and verifiable register allocation across GPU architectures. VeriLocc fine-tunes an LLM to translate intermediate representations (MIRs) into target-specific register assignments, aided by static analysis for cross-architecture normalization and generalization and a verifier-guided regeneration loop to ensure correctness. Evaluated on matrix multiplication (GEMM) and multi-head attention (MHA), VeriLocc achieves 85-99% single-shot accuracy and near-100% pass@100. Case study shows that VeriLocc discovers more performant assignments than expert-tuned libraries, outperforming rocBLAS by over 10% in runtime.

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