High-Performance Contraction of Quantum Circuits for Riemannian Optimization

• URL: http://arxiv.org/abs/2506.23775v1
• Date: Mon, 30 Jun 2025 12:18:16 GMT
• Title: High-Performance Contraction of Quantum Circuits for Riemannian Optimization
• Authors: Fabian Putterer, Max M. Zumpe, Isabel Nha Minh Le, Qunsheng Huang, Christian B. Mendl,
• Abstract summary: This work focuses on optimizing the gates of a quantum circuit with a given topology to approximate the unitary time evolution governed by a Hamiltonian.<n>Our key technical contribution is a matrix-free algorithmic framework that avoids the explicit construction and storage of large unitary matrices acting on the whole Hilbert space.<n>We benchmark our implementation on the Fermi-Hubbard model with up to 16 sites, demonstrating a nearly linear parallelization speed-up with up to 112 CPU threads.
• Score: 0.0
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: This work focuses on optimizing the gates of a quantum circuit with a given topology to approximate the unitary time evolution governed by a Hamiltonian. Recognizing that unitary matrices form a mathematical manifold, we employ Riemannian optimization methods -- specifically the Riemannian trust-region algorithm -- which involves second derivative calculations with respect to the gates. Our key technical contribution is a matrix-free algorithmic framework that avoids the explicit construction and storage of large unitary matrices acting on the whole Hilbert space. Instead, we evaluate all quantities as sums over state vectors, assuming that these vectors can be stored in memory. We develop HPC-optimized kernels for applying gates to state vectors and for the gradient and Hessian computation. Further improvements are achieved by exploiting sparsity structures due to Hamiltonian conservation laws, such as parity conservation, and lattice translation invariance. We benchmark our implementation on the Fermi-Hubbard model with up to 16 sites, demonstrating a nearly linear parallelization speed-up with up to 112 CPU threads. Finally, we compare our implementation with an alternative matrix product operator-based approach.

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