When Routers, Switches and Interconnects Compute: A processing-in-interconnect Paradigm for Scalable Neuromorphic AI

• URL: http://arxiv.org/abs/2508.19548v1
• Date: Wed, 27 Aug 2025 03:46:46 GMT
• Title: When Routers, Switches and Interconnects Compute: A processing-in-interconnect Paradigm for Scalable Neuromorphic AI
• Abstract summary: We show that operations required for typical AI workloads can be mapped onto delays, causality, time-outs, packet drop, and broadcast operations.<n>We show that existing buffering and traffic-shaping embedded algorithms can be leveraged to implement neuron models and synaptic operations.<n>We predict that by leveraging trends in interconnect technology, a pi2 architecture can be more easily scaled to execute brain-scale AI inference workloads.
• Score: 14.546627978614707
• License: http://creativecommons.org/licenses/by-nc-nd/4.0/
• Abstract: Routing, switching, and the interconnect fabric are essential for large-scale neuromorphic computing. While this fabric only plays a supporting role in the process of computing, for large AI workloads it ultimately determines energy consumption and speed. In this paper, we address this bottleneck by asking: (a) What computing paradigms are inherent in existing routing, switching, and interconnect systems, and how can they be used to implement a processing-in-Interconnect (\pi^2) computing paradigm? and (b) leveraging current and future interconnect trends, how will a \pi^2 system's performance scale compared to other neuromorphic architectures? For (a), we show that operations required for typical AI workloads can be mapped onto delays, causality, time-outs, packet drop, and broadcast operations -- primitives already implemented in packet-switching and packet-routing hardware. We show that existing buffering and traffic-shaping embedded algorithms can be leveraged to implement neuron models and synaptic operations. Additionally, a knowledge-distillation framework can train and cross-map well-established neural network topologies onto $\pi^2$ without degrading generalization performance. For (b), analytical modeling shows that, unlike other neuromorphic platforms, the energy scaling of $\pi^2$ improves with interconnect bandwidth and energy efficiency. We predict that by leveraging trends in interconnect technology, a \pi^2 architecture can be more easily scaled to execute brain-scale AI inference workloads with power consumption levels in the range of hundreds of watts.

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