Practical Fidelity Limits of Toffoli Gates in Superconducting Quantum Processors

• URL: http://arxiv.org/abs/2509.05395v1
• Date: Fri, 05 Sep 2025 12:58:13 GMT
• Title: Practical Fidelity Limits of Toffoli Gates in Superconducting Quantum Processors
• Abstract summary: High-fidelity multi-qubit gates are a critical resource for near-term quantum computing.<n>We present a hardware-aware characterization of the Toffoli gate on IBM's 127-qubit superconducting quantum processors.
• Score: 0.0
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: High-fidelity multi-qubit gates are a critical resource for near-term quantum computing, as they underpin the execution of both quantum algorithms and fault-tolerant protocols. The Toffoli gate (CCNOT), in particular, plays a central role in quantum error correction and quantum arithmetic, yet its efficient implementation on current quantum hardware remains limited by noise and connectivity constraints. In this work, we present a hardware-aware characterization of the Toffoli gate using optimized, connectivity-compliant decompositions executed on IBM's 127-qubit superconducting quantum processors. Our study integrates state preparation, gate synthesis, and quantum state/process tomography (QST/QPT) to evaluate fidelity across three distinct classes of input states: Greenberger-Horne-Zeilinger (GHZ), W, and the uniform superposition of all three-qubit computational basis states -- under noise-free simulation, noise-aware emulation, and real hardware execution. For GHZ states, we report state fidelities of 98.442% (noise-free simulation), 81.470% (noise-aware quantum emulation), and 56.368% (real quantum hardware). For W states, state fidelities are 98.739%, 79.900%, and 63.689%, respectively, and for the uniform superposition state, we observe state fidelities of 99.490%, 85.469%, and 61.161%. Comparative QPT experiments yield process fidelities of 98.976% (noise-free) and 80.160% (noise-aware emulation). Our results empirically characterize state-dependent error patterns in multi-qubit circuits and quantify trade-offs between gate decomposition strategies and native hardware performance, offering practical insights for scalable, hardware-efficient quantum circuit design.

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