Hybrid unary-binary design for multiplier-less printed Machine Learning classifiers

• URL: http://arxiv.org/abs/2509.15316v1
• Date: Thu, 18 Sep 2025 18:02:24 GMT
• Title: Hybrid unary-binary design for multiplier-less printed Machine Learning classifiers
• Authors: Giorgos Armeniakos, Theodoros Mantzakidis, Dimitrios Soudris,
• Abstract summary: Printed Electronics (PE) provide a flexible, cost-efficient alternative to silicon for implementing machine learning (ML) circuits.<n>This work explores alternative arithmetic and a hybrid unary-binary architecture that removes costly encoders and enables efficient, multiplier-less execution of classifiers.<n> Evaluation on six datasets shows average reductions of 46% in area and 39% in power, with minimal accuracy loss, surpassing other state-of-the-art designs.
• Score: 3.0435742174040548
• License: http://creativecommons.org/licenses/by-nc-nd/4.0/
• Abstract: Printed Electronics (PE) provide a flexible, cost-efficient alternative to silicon for implementing machine learning (ML) circuits, but their large feature sizes limit classifier complexity. Leveraging PE's low fabrication and NRE costs, designers can tailor hardware to specific ML models, simplifying circuit design. This work explores alternative arithmetic and proposes a hybrid unary-binary architecture that removes costly encoders and enables efficient, multiplier-less execution of MLP classifiers. We also introduce architecture-aware training to further improve area and power efficiency. Evaluation on six datasets shows average reductions of 46% in area and 39% in power, with minimal accuracy loss, surpassing other state-of-the-art MLP designs.

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