From RISC-V Cores to Neuromorphic Arrays: A Tutorial on Building Scalable Digital Neuromorphic Processors

• URL: http://arxiv.org/abs/2512.00113v1
• Date: Thu, 27 Nov 2025 14:14:23 GMT
• Title: From RISC-V Cores to Neuromorphic Arrays: A Tutorial on Building Scalable Digital Neuromorphic Processors
• Abstract summary: Digital neuromorphic processors are emerging as a promising computing substrate for low-power, always-on EdgeAI applications.<n>This tutorial paper outlines the main architectural design principles behind fully digital neuromorphic processors.
• Score: 0.37863160479533026
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Digital neuromorphic processors are emerging as a promising computing substrate for low-power, always-on EdgeAI applications. In this tutorial paper, we outline the main architectural design principles behind fully digital neuromorphic processors and illustrate them using the SENECA platform as a running example. Starting from a flexible array of tiny RISC-V processing cores connected by a simple Network-on-Chip (NoC), we show how to progressively evolve the architecture: from a baseline event-driven implementation of fully connected networks, to versions with dedicated Neural Processing Elements (NPEs) and a loop controller that offloads fine-grained control from the general-purpose cores. Along the way, we discuss software and mapping techniques such as spike grouping, event-driven depth-first convolution for convolutional networks, and hard-attention style processing for high-resolution event-based vision. The focus is on architectural trade-offs, performance and energy bottlenecks, and on leveraging flexibility to incrementally add domain-specific acceleration. This paper assumes familiarity with basic neuromorphic concepts (spikes, event-driven computation, sparse activation) and deep neural network workloads. It does not present new experimental results; instead, it synthesizes and contextualizes findings previously reported in our SENECA publications to provide a coherent, step-by-step architectural perspective for students and practitioners who wish to design their own digital neuromorphic processors.

Related papers

• Heterogeneous SoC Integrating an Open-Source Recurrent SNN Accelerator for Neuromorphic Edge Computing on FPGA [2.2940088641992697]
  The spread of digital neuromorphic hardware is slowed down by the prohibitive costs that the silicon tape out of circuits brings.<n>We present an heterogeneous System-on-Chip (SoC) where the operations of ReckOn, a Recurrent SNN accelerator, are managed through the integration with traditional processors.
  arXiv  Detail & Related papers  (2026-05-12T14:55:21Z)
• Kirchhoff-Inspired Neural Networks for Evolving High-Order Perception [51.28469959548178]
  We propose the Kirchhoff-Inspired Neural Network (KINN), a state-variable-based network architecture constructed based on Kirchhoff's current law.<n>KINN derives numerically stable state updates from fundamental ordinary differential equations, enabling the explicit decoupling and encoding of higher-order evolutionary components.
  arXiv  Detail & Related papers  (2026-03-25T06:17:31Z)
• Towards Cold-Start Drafting and Continual Refining: A Value-Driven Memory Approach with Application to NPU Kernel Synthesis [68.7701048879757]
  EvoKernel is a self-evolving agentic framework that automates the lifecycle of kernel synthesis.<n>It learns stage-specific Q-values that prioritize experiences based on their contribution to the current objective.<n>It improves models' correctness from 11.0% to 83.0% and a median speedup of 3.60x over initial drafts.
  arXiv  Detail & Related papers  (2026-03-11T14:57:06Z)
• NeuroCoreX: An Open-Source FPGA-Based Spiking Neural Network Emulator with On-Chip Learning [0.0]
  Spiking Neural Networks (SNNs) are computational models inspired by the structure and dynamics of biological neuronal networks.<n>NeuroCoreX is an FPGA-based emulator designed for the flexible co-design and testing of SNNs.
  arXiv  Detail & Related papers  (2025-06-17T03:02:04Z)
• A Realistic Simulation Framework for Analog/Digital Neuromorphic Architectures [73.65190161312555]
  ARCANA is a software spiking neural network simulator designed to account for the properties of mixed-signal neuromorphic circuits.<n>We show how the results obtained provide a reliable estimate of the behavior of the spiking neural network trained in software, once deployed in hardware.
  arXiv  Detail & Related papers  (2024-09-23T11:16:46Z)
• Contrastive Learning in Memristor-based Neuromorphic Systems [55.11642177631929]
  Spiking neural networks have become an important family of neuron-based models that sidestep many of the key limitations facing modern-day backpropagation-trained deep networks. In this work, we design and investigate a proof-of-concept instantiation of contrastive-signal-dependent plasticity (CSDP), a neuromorphic form of forward-forward-based, backpropagation-free learning.
  arXiv  Detail & Related papers  (2024-09-17T04:48:45Z)
• NNsight and NDIF: Democratizing Access to Open-Weight Foundation Model Internals [58.83169560132308]
  We introduce NNsight and NDIF, technologies that work in tandem to enable scientific study of the representations and computations learned by very large neural networks.
  arXiv  Detail & Related papers  (2024-07-18T17:59:01Z)
• Towards Scalable and Versatile Weight Space Learning [51.78426981947659]
  This paper introduces the SANE approach to weight-space learning. Our method extends the idea of hyper-representations towards sequential processing of subsets of neural network weights.
  arXiv  Detail & Related papers  (2024-06-14T13:12:07Z)
• Principled Architecture-aware Scaling of Hyperparameters [69.98414153320894]
  Training a high-quality deep neural network requires choosing suitable hyperparameters, which is a non-trivial and expensive process. In this work, we precisely characterize the dependence of initializations and maximal learning rates on the network architecture. We demonstrate that network rankings can be easily changed by better training networks in benchmarks.
  arXiv  Detail & Related papers  (2024-02-27T11:52:49Z)
• Mechanistic Neural Networks for Scientific Machine Learning [58.99592521721158]
  We present Mechanistic Neural Networks, a neural network design for machine learning applications in the sciences. It incorporates a new Mechanistic Block in standard architectures to explicitly learn governing differential equations as representations. Central to our approach is a novel Relaxed Linear Programming solver (NeuRLP) inspired by a technique that reduces solving linear ODEs to solving linear programs.
  arXiv  Detail & Related papers  (2024-02-20T15:23:24Z)
• Free-Space Optical Spiking Neural Network [0.0]
  We introduce the Free-space Optical deep Spiking Convolutional Neural Network (OSCNN) This novel approach draws inspiration from computational models of the human eye. Our results demonstrate promising performance with minimal latency and power consumption compared to their electronic ONN counterparts.
  arXiv  Detail & Related papers  (2023-11-08T09:41:14Z)
• CP-CNN: Core-Periphery Principle Guided Convolutional Neural Network [9.015666133509857]
  We implement the core-periphery principle in the design of network wiring patterns and the sparsification of the convolution operation. Our work contributes to the growing field of brain-inspired AI by incorporating insights from the human brain into the design of neural networks.
  arXiv  Detail & Related papers  (2023-03-27T03:59:43Z)
• Fluid Batching: Exit-Aware Preemptive Serving of Early-Exit Neural Networks on Edge NPUs [74.83613252825754]
  "smart ecosystems" are being formed where sensing happens concurrently rather than standalone. This is shifting the on-device inference paradigm towards deploying neural processing units (NPUs) at the edge. We propose a novel early-exit scheduling that allows preemption at run time to account for the dynamicity introduced by the arrival and exiting processes.
  arXiv  Detail & Related papers  (2022-09-27T15:04:01Z)
• Bottom-up and top-down approaches for the design of neuromorphic processing systems: Tradeoffs and synergies between natural and artificial intelligence [3.874729481138221]
  Moore's law has driven exponential computing power expectations, its nearing end calls for new avenues for improving the overall system performance. One of these avenues is the exploration of alternative brain-inspired computing architectures that aim at achieving the flexibility and computational efficiency of biological neural processing systems. We provide a comprehensive overview of the field, highlighting the different levels of granularity at which this paradigm shift is realized.
  arXiv  Detail & Related papers  (2021-06-02T16:51:45Z)
• Large-scale neuromorphic optoelectronic computing with a reconfigurable diffractive processing unit [38.898230519968116]
  We propose an optoelectronic reconfigurable computing paradigm by constructing a diffractive processing unit. It can efficiently support different neural networks and achieve a high model complexity with millions of neurons. Our prototype system built with off-the-shelf optoelectronic components surpasses the performance of state-of-the-art graphics processing units.
  arXiv  Detail & Related papers  (2020-08-26T16:34:58Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.