Related papers: In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss

In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss

URL: http://arxiv.org/abs/2512.03461v1
Date: Wed, 03 Dec 2025 05:30:10 GMT
Title: In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss
Authors: Sanwar Ahmed Ovy, Jiahui Duan, Md Ashraful Islam Romel, Franz Muller, Thomas Kampfe, Kai Ni, Sumitha George,
Abstract summary: This work proposes an ultra-dense single-transistor encrypted cell using ferroelectric FETs (FeFETs)<n>It is the first to eliminate the two-memory-devices-per-encrypted-cell requirement in XOR-based schemes.<n>Our analysis on a 128x128-bit array shows 2x higher encryption/decryption throughput than prior FeFET work and 45.2x/14.12x improvement over AES.
Score: 1.6138201450126488
License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
Abstract: Non-volatile memories (NVMs) offer negligible leakage power consumption, high integration density, and data retention, but their non-volatility also raises the risk of data exposure. Conventional encryption techniques such as the Advanced Encryption Standard (AES) incur large area overheads and performance penalties, motivating lightweight XOR-based in-situ encryption schemes with low area and power requirements. This work proposes an ultra-dense single-transistor encrypted cell using ferroelectric FET (FeFET) devices, which, to our knowledge, is the first to eliminate the two-memory-devices-per-encrypted-cell requirement in XOR-based schemes, enabling encrypted memory arrays to maintain the same number of storage devices as unencrypted arrays. The key idea is an in-memory single-FeFET XOR scheme, where the ciphertext is encoded in the device threshold voltage and leverages the direction-dependent current flow of the FeFET for single-cycle decryption; eliminating complementary bit storage also removes the need for two write cycles, allowing faster encryption. We extend the approach to multi-level-cell (MLC) FeFETs to store multiple bits per transistor. We validate the proposed idea through both simulation and experimental evaluations. Our analysis on a 128x128-bit array shows 2x higher encryption/decryption throughput than prior FeFET work and 45.2x/14.12x improvement over AES, while application-level evaluations using neural-network benchmarks demonstrate average latency reductions of 50% and 95% compared to prior FeFET-based and AES-based schemes, respectively.

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