Geometry- and Topology-Informed Quantum Computing: From States to Real-Time Control with FPGA Prototypes

• URL: http://arxiv.org/abs/2601.09556v1
• Date: Wed, 14 Jan 2026 15:18:29 GMT
• Title: Geometry- and Topology-Informed Quantum Computing: From States to Real-Time Control with FPGA Prototypes
• Authors: Gunhee Cho,
• Abstract summary: This book gives a geometry-first, hardware-aware route through quantum-information-aware systems.<n>Part 1 develops the backbone so evolution can be read as motion on curved spaces and measurement as statistics.<n>Part 2 reframes circuits as dataflow graphs: measurement outcomes are parsed, aggregated, and reduced to small linear- algebra updates.<n>Part 3 treats multi-qubit structure and entanglement as geometry and computation, including teleportation.<n>Part 4 focuses on topological error correction and real-time decoding.
• Score: 1.0152838128195467
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: This book gives a geometry-first, hardware-aware route through quantum-information workflows, with one goal: connect states, circuits, and measurement to deterministic classical pipelines that make hybrid quantum systems run. Part 1 develops the backbone (essential linear algebra, the Bloch-sphere viewpoint, differential-geometric intuition, and quantum Fisher information geometry) so evolution can be read as motion on curved spaces and measurement as statistics. Part 2 reframes circuits as dataflow graphs: measurement outcomes are parsed, aggregated, and reduced to small linear-algebra updates that schedule the next pulses, highlighting why low-latency, low-jitter streaming matters. Part 3 treats multi-qubit structure and entanglement as geometry and computation, including teleportation, superdense coding, entanglement detection, and Shor's algorithm via quantum phase estimation. Part 4 focuses on topological error correction and real-time decoding (Track A): stabilizer codes, surface-code decoding as "topology -> graph -> algorithm", and Union-Find decoders down to microarchitectural/RTL constraints, with verification, fault injection, and host/control-stack integration under product metrics (bounded latency, p99 tails, fail-closed policies, observability). Optional Track C covers quantum cryptography and streaming post-processing (BB84/E91, QBER/abort rules, privacy amplification, and zero-knowledge/post-quantum themes), emphasizing FSMs, counters, and hash pipelines. Appendices provide visualization-driven iCEstick labs (switch-to-bit conditioning, fixed-point phase arithmetic, FSM sequencing, minimal control ISAs), bridging principles to implementable systems.

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