Focus Session: LLM4PQC -- An Agentic Framework for Accurate and Efficient Synthesis of PQC Cores

• URL: http://arxiv.org/abs/2602.09919v1
• Date: Tue, 10 Feb 2026 15:53:37 GMT
• Title: Focus Session: LLM4PQC -- An Agentic Framework for Accurate and Efficient Synthesis of PQC Cores
• Abstract summary: The design of post-quantum cryptography (PQC) hardware is a complex and hierarchical process.<n>A primary bottleneck is the conversion of PQC reference codes from C to high-level synthesis (HLS) specifications.<n>Here, we propose LLM4PQC, an agentic framework that synthesizes high-level PQC specifications and reference C codes into synthesizable C code.
• Score: 12.18204758079849
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: The design of post-quantum cryptography (PQC) hardware is a complex and hierarchical process with many challenges. A primary bottleneck is the conversion of PQC reference codes from C to high-level synthesis (HLS) specifications, which requires extensive manual refactoring [1]-[3]. Another bottleneck is the scalability of synthesis for complex PQC primitives, including number theoretic transform (NTT) accelerators and wide memory interfaces. While large language models (LLMs) have shown remarkable results for coding in general-purpose languages like Python, coding for hardware design is more challenging; feedback-driven and agentic integration are key principles of successful state-of-the-art approaches. Here, we propose LLM4PQC, an LLM-based agentic framework that refactors high-level PQC specifications and reference C codes into HLS-ready and synthesizable C code. Our framework generates and verifies the resulting RTL code. For correctness, we leverage a hierarchy of checks, covering fast C compilation and simulation as well as RTL simulation. Case studies on NIST PQC reference designs demonstrate a reduction in manual effort and accelerated design-space exploration compared to traditional flows. Overall, LLM4PQC provides a powerful and efficient pathway for synthesizing complex hardware accelerators.

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