Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder

• URL: http://arxiv.org/abs/2605.04892v1
• Date: Wed, 06 May 2026 13:24:10 GMT
• Title: Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder
• Abstract summary: We report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder.<n>We experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor.<n>We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding.
• Score: 11.81591184245689
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Quantum error correction (QEC) is essential for achieving low error rates required for fault-tolerant quantum computation. In stabilizer-based codes such as the surface code, errors are inferred from repeated syndrome measurements and corrected by a classical decoder. To prevent error accumulation, decoding must be performed with both high throughput and low latency to keep pace with the QEC cycle and enable real-time feedback for universal logical operations. Here we report a hardware-integrated control architecture featuring an FPGA-based neural-network (NN) decoder and experimentally demonstrate real-time surface-code (distance-3) QEC on a superconducting quantum processor. The system achieves a deterministic closed-loop latency of 550 ns, including 124 ns for NN decoding, enabling feedback corrections within a 1.25 us QEC cycle. We show that real-time decoding and feedback correction achieve logical performance comparable to offline decoding while maintaining robustness against varying error conditions. We further demonstrate mid-circuit feedback correction in non-Clifford logical circuits, where Pauli-frame updating alone becomes insufficient. Our results establish a low-latency hardware architecture for embedded QEC control and provide a pathway towards scalable fault-tolerant quantum computing systems.

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