General circuit mapping algorithm for neutral atom quantum computers

• URL: http://arxiv.org/abs/2606.20503v1
• Date: Thu, 18 Jun 2026 17:21:23 GMT
• Title: General circuit mapping algorithm for neutral atom quantum computers
• Abstract summary: Neutral atom quantum computers (NAQC) are emerging as a promising, scalable quantum computing platform.<n> circuit execution often requires physically moving qubits, making compilation a critical optimization challenge.<n>We propose a circuit independent mathematical framework built on graph-theoretic optimization that determines the minimal number of required qubit transfers.
• Score: 1.047947389293086
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Neutral atom quantum computers (NAQC) are emerging as a promising, scalable quantum computing platform because of their long qubit coherence, flexible qubit arrangement, and multiqubit gate capabilities. However, circuit execution often requires physically moving qubits, making compilation a critical optimization challenge. We propose a circuit independent mathematical framework built on graph-theoretic combinatorial optimization that determines the minimal number of required qubit transfers. This model captures spatial constraints specific to NAQC platforms with zone-limited gate operations and multi-qubit gates. From this framework, we encode the qubit mapping problem as a nonlinear integer program and solve it using a genetic algorithm, enabling trade-offs between minimizing the total traveled distance and the number of parallel transfer operations. Compared to the state-of-the-art scalable compiler for zoned architectures, our approach consistently finds fewer transfers. Depending on the optimization focus, our method produces shorter traveled distances or fewer parallel transfer operations. This work provides both theoretical guaranties and a practical tool for efficient, architecture-aware quantum circuit compilation. As a result, practitioners can generate hardware-aware mappings that reduce movement-induced errors and better exploit atom transfer parallelism, directly improving execution efficiency on NAQC devices.

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