Mapping quantum circuits to modular architectures with QUBO

• URL: http://arxiv.org/abs/2305.06687v1
• Date: Thu, 11 May 2023 09:45:47 GMT
• Title: Mapping quantum circuits to modular architectures with QUBO
• Authors: Medina Bandic, Luise Prielinger, Jonas N\"u{\ss}lein, Anabel Ovide, Santiago Rodrigo, Sergi Abadal, Hans van Someren, Gayane Vardoyan, Eduard Alarcon, Carmen G. Almudever and Sebastian Feld
• Abstract summary: In multi-core architectures, it is crucial to minimize the amount of communication between cores when executing an algorithm. We propose for the first time a Quadratic Unconstrained Binary Optimization technique to encode the problem and the solution. Our method showed promising results and performed exceptionally well with very dense and highly-parallelized circuits.
• Score: 3.0148208709026005
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Modular quantum computing architectures are a promising alternative to monolithic QPU (Quantum Processing Unit) designs for scaling up quantum devices. They refer to a set of interconnected QPUs or cores consisting of tightly coupled quantum bits that can communicate via quantum-coherent and classical links. In multi-core architectures, it is crucial to minimize the amount of communication between cores when executing an algorithm. Therefore, mapping a quantum circuit onto a modular architecture involves finding an optimal assignment of logical qubits (qubits in the quantum circuit) to different cores with the aim to minimize the number of expensive inter-core operations while adhering to given hardware constraints. In this paper, we propose for the first time a Quadratic Unconstrained Binary Optimization (QUBO) technique to encode the problem and the solution for both qubit allocation and inter-core communication costs in binary decision variables. To this end, the quantum circuit is split into slices, and qubit assignment is formulated as a graph partitioning problem for each circuit slice. The costly inter-core communication is reduced by penalizing inter-core qubit communications. The final solution is obtained by minimizing the overall cost across all circuit slices. To evaluate the effectiveness of our approach, we conduct a detailed analysis using a representative set of benchmarks having a high number of qubits on two different multi-core architectures. Our method showed promising results and performed exceptionally well with very dense and highly-parallelized circuits that require on average 0.78 inter-core communications per two-qubit gate.

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