2.5D Root of Trust: Securing the Chiplet Ecosystem

• URL: http://arxiv.org/abs/2606.22198v1
• Date: Sat, 20 Jun 2026 19:19:54 GMT
• Title: 2.5D Root of Trust: Securing the Chiplet Ecosystem
• Abstract summary: semiconductor industry is transitioning from monolithic systems-on-chip to heterogeneous, multi-vendor 2.5D chiplet ecosystems integrated via silicon interposers.<n>Integrating chiplets from untrusted foundries and design houses introduces vulnerabilities to hardware Trojans, IP piracy, and system-level communication exploits.<n>This paper surveys state-of-the-art security strategies for interposer-based 2.5D integration.
• Score: 4.903182581735334
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: The semiconductor industry is rapidly transitioning from monolithic systems-on-chip toward heterogeneous, multi-vendor 2.5D chiplet ecosystems integrated via silicon interposers. While this paradigm shift offers immense benefits in yield, cost, and time-to-market, it radically expands the attack surface. Integrating chiplets from untrusted foundries and design houses introduces vulnerabilities to hardware Trojans, IP piracy, and system-level communication exploits. Critically, chip-level security features and conventional Root of Trust (RoT) proposals are insufficient in this context: any component, including the interconnect fabric itself, may be sourced from an untrusted vendor. This perspective paper surveys state-of-the-art security strategies for interposer-based 2.5D integration, focusing on three threat categories: interconnect attacks (snooping, spoofing, and man-in-the-middle), cache coherence exploits including complex forging attacks, and microarchitectural side-channel threats. We examine design-time defenses via 2.5D split manufacturing and, more crucially, runtime defenses that establish an active interposer as a physically isolated 2.5D RoT. By embedding so-called transaction monitors and coherence message checkers within the trusted interposer fabric, the system enforces memory access permissions by construction and neutralizes coherence-level attacks without need for modifying/securing the commodity chiplets. Finally, we review the EDA flows required to realize these defenses and show they concurrently improve power and signal integrity while reducing overall system footprint.

Related papers

• Hardware Design and Security in the Era of Chiplets and LLMs [12.304805014484423]
  The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models into Electronic Design Automation flows.<n>This paper provides a unified analysis of these frontiers, ranging from attacks on chiplet systems across architectural, logical, and physical levels, to various exploits against LLM-driven EDA pipelines.
  arXiv  Detail & Related papers  (2026-08-05T17:09:13Z)
• Safety in Self-Evolving LLM Agent Systems: Threats, Amplification, and Case Studies [62.65225104423404]
  Self-evolving agent systems introduce a qualitatively new threat landscape in which adversarial influences become permanently encoded.<n>We present a systematic security and privacy analysis organized around the Module-Lifecycle Attack Surface matrix.<n>Our findings establish that self-evolution converts every known attack category from session-bounded to lineage-persistent.
  arXiv  Detail & Related papers  (2026-06-22T09:23:50Z)
• The End of Trust: How Agentic AI Breaks Security Assumptions [45.13166202592558]
  We introduce the Infinite Impostor, an attack model in which an autonomous agent interposes itself between two parties who already trust each other.<n>We propose a suspect-by-default paradigm that shifts security from authenticating actors to evaluating actions.
  arXiv  Detail & Related papers  (2026-05-14T21:30:06Z)
• Multi-Agent-Driven Cognitive Secure Communications in Satellite-Terrestrial Networks [58.70163955407538]
  Malicious eavesdroppers pose a serious threat to private information via satellite-terrestrial networks (STNs)<n>We propose a cognitive secure communication framework driven by multiple agents that coordinates spectrum scheduling and protection through real-time sensing.<n>We exploit generative adversarial networks to produce adversarial matrices, and employ learning-aided power control to set real and adversarial signal powers for protection layer.
  arXiv  Detail & Related papers  (2026-01-06T10:30:41Z)
• OpenRT: An Open-Source Red Teaming Framework for Multimodal LLMs [36.57820295876294]
  We introduce OpenRT, a unified, modular, and high- throughput red-teaming framework for MLLM safety evaluation.<n>At its core, OpenRT architects a paradigm shift in automated red-teaming by introducing an adversarial kernel that enables modular separation across five dimensions.<n>Our framework integrates 37 diverse attack methodologies, spanning white-box gradients, multi-modal perturbations, and sophisticated multi-agent evolutionary strategies.
  arXiv  Detail & Related papers  (2026-01-04T16:41:33Z)
• Secure Tug-of-War (SecTOW): Iterative Defense-Attack Training with Reinforcement Learning for Multimodal Model Security [63.41350337821108]
  We propose Secure Tug-of-War (SecTOW) to enhance the security of multimodal large language models (MLLMs)<n>SecTOW consists of two modules: a defender and an auxiliary attacker, both trained iteratively using reinforcement learning (GRPO)<n>We show that SecTOW significantly improves security while preserving general performance.
  arXiv  Detail & Related papers  (2025-07-29T17:39:48Z)
• Enabling Security on the Edge: A CHERI Compartmentalized Network Stack [42.78181795494584]
  CHERI provides strong security from the hardware level by enabling fine-grained compartmentalization and memory protection.<n>Our case study examines the trade-offs of isolating applications, TCP/IP libraries, and network drivers on a CheriBSD system deployed on the Arm Morello platform.
  arXiv  Detail & Related papers  (2025-07-07T09:37:59Z)
• SAFE-SiP: Secure Authentication Framework for System-in-Package Using Multi-party Computation [0.0]
  Chiplet-based heterogeneous integration is transforming the semiconductor, AI, and high-performance computing industries.<n>Current solutions often depend on dedicated security chiplets or changes to the timing flow, which assume a trusted SiP integrator.<n>We present SAFE-SiP, a scalable authentication framework that garbles chiplet signatures and uses MPC for verifying integrity.
  arXiv  Detail & Related papers  (2025-05-13T22:36:17Z)
• ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification [3.766999700958066]
  This paper presents textitChipletQuake, a novel on-chiplet framework for verifying the physical security and integrity of adjacent chiplets during the post-silicon stage.<n>By sensing the impedance of the power delivery network (PDN) of the system, textitChipletQuake detects tamper events without requiring any direct signal interface or additional hardware components.
  arXiv  Detail & Related papers  (2025-04-28T02:10:12Z)
• A Comprehensive Framework for Building Highly Secure, Network-Connected Devices: Chip to App [1.4732811715354452]
  This paper proposes a holistic approach to securing network-connected devices.<n>At the hardware level, we focus on secure key management, reliable random number generation, and protecting critical assets.<n>For secure communication, we emphasize TLS 1.3 and optimized cipher suites tailored for both standard and resource-constrained devices.
  arXiv  Detail & Related papers  (2025-01-23T14:44:34Z)
• ACRIC: Securing Legacy Communication Networks via Authenticated Cyclic Redundancy Integrity Check [98.34702864029796]
  Recent security incidents in safety-critical industries exposed how the lack of proper message authentication enables attackers to inject malicious commands or alter system behavior.<n>These shortcomings have prompted new regulations that emphasize the pressing need to strengthen cybersecurity.<n>We introduce ACRIC, a message authentication solution to secure legacy industrial communications.
  arXiv  Detail & Related papers  (2024-11-21T18:26:05Z)
• Physical Layer Deception with Non-Orthogonal Multiplexing [52.11755709248891]
  We propose a novel framework of physical layer deception (PLD) to actively counteract wiretapping attempts.<n>PLD combines PLS with deception technologies to actively counteract wiretapping attempts.<n>We prove the validity of the PLD framework with in-depth analyses and demonstrate its superiority over conventional PLS approaches.
  arXiv  Detail & Related papers  (2024-06-30T16:17:39Z)
• SCARF: Securing Chips with a Robust Framework against Fabrication-time Hardware Trojans [1.8980236415886387]
  Hardware Trojans (HTs) can be introduced during IC fabrication. We propose a comprehensive approach to enhance IC security from front-end to back-end stages of design.
  arXiv  Detail & Related papers  (2024-02-19T14:18:08Z)
• Designing Secure Interconnects for Modern Microelectronics: From SoCs to Emerging Chiplet-Based Architectures [0.0]
  Research focuses on securing Network-on-Chip (NoC) interconnects in System-on-Chip (SoC) architectures.<n>Research builds on two methodologies: ObNoCs and POTENT.<n>New challenges, such as safeguarding inter-chiplet communication and interposer design, are addressed through enhanced obfuscation, authentication, and encryption mechanisms.
  arXiv  Detail & Related papers  (2023-07-11T21:49:45Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.