Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices

• URL: http://arxiv.org/abs/2607.18149v1
• Date: Mon, 20 Jul 2026 16:49:30 GMT
• Title: Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices
• Abstract summary: Real-time EEG classification on edge devices is bottlenecked by the floating-point arithmetic of conventional neural networks.<n>We investigated Differentiable Logic Gate Networks (Diff-Logic) as a hardware-native alternative.<n>Our results establish logic-based neural architectures as a practical paradigm for resource-constrained brain-computer interfaces.
• Score: 0.0
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Real-time EEG classification on edge devices is bottlenecked by the floating-point arithmetic of conventional neural networks. We investigated Differentiable Logic Gate Networks (Diff-Logic) as a hardware-native alternative that compiles models into pure Boolean circuits executable via bitwise CPU operations. Through rigorous iso-parameter experiments across four EEG datasets spanning two classification tasks, binary dementia detection and 3-class emotion recognition, we compared Diff-Logic against matched-capacity Multi-Layer Perceptron (MLP) and Binarized Neural Network (BNN) baselines at four complexity tiers (50k-500k parameters). On dementia screening, Diff-Logic achieved 80.2% Macro F1, outperforming the MLP baseline by 6.8%. On emotion recognition, the MLP retained a moderate performance advantage but incurred a 2.3$\times$ higher latency and 14$\times$ larger model size when deployed on a power-constrained (7W) Nvidia Jetson Orin Nano CPU (Single-core). Critically, Diff-Logic inference time remained nearly constant across a 10$\times$ increase in model scale, achieving a peak speedup of 2.9$\times$ over MLPs at the largest complexity tier. Our results establish logic-based neural architectures as a practical paradigm for resource-constrained brain-computer interfaces, achieving competitive or superior performance while natively satisfying the latency and memory constraints of portable edge deployment. Code is available on GitHub: https://github.com/Shyamal-Dharia/eeg-difflogic

Related papers

• Scalability Analysis of Distributed Kolmogorov-Arnold Network Training on High-Performance Computing Systems [0.2730969268472861]
  Kolmogorov-Arnold Networks (KANs) replace the fixed activation functions and linear weights of Multi-Layer Perceptrons (MLPs)<n>This paper presents an empirical scalability study of data-parallel KAN training on multi-node, multi-GPU high-performance computing infrastructure.<n>Experiments were conducted on the FinisTerrae III supercomputer using up to 8 NVIDIA A100 GPUs across 4 nodes with PyTorch Distributed Data Parallel (DDP)
  arXiv  Detail & Related papers  (2026-09-07T16:45:20Z)
• Long-Range Indirect Control-Flow Prediction in Stripped Binaries via Dual Virtual Hubs and Multi-Task Graph Learning [44.79384874347874]
  We present ICFlowNet, a unified framework for long-range ICF prediction in stripped binaries.<n>ICFlowNet introduces candidate-aware Dual Virtual Hubs, a Global Code Hub and a Global Data Hub.<n>We also develop a leakage-aware, noise-controlled pipeline with package-level splits, function-level mnemonic-hash deduplication, and a clean test protocol.
  arXiv  Detail & Related papers  (2026-09-03T02:17:23Z)
• On the Design of Qwen3.8-Next Architecture: Evaluation, Efficiency, and Training Stability [57.03393882933515]
  We describe the architecture and ablations of Qwen3.8-Flash-Next, a sparse mixture-of-experts model with 125B parameters, 6B activated per token, and 51B parameters of n-gram embedding tables held off the accelerator.<n>On fourteen pre-training benchmarks the model leads the 397B-A17B predecessor on eight and trails it on the rest by at most 2.6 points, at 1/3 the activated parameters, 1/3 the training tokens, and roughly 1/9 the training FLOPs.
  arXiv  Detail & Related papers  (2026-08-31T06:35:07Z)
• BoltNet: An Ultra-Lightweight Convolutional Network for On-Device Plant Species Identification [3.860597465886636]
  BoltNet is an ultra-lightweight fully convolutional architecture combining a Spatial Redistribution Bottleneck and Logit PreSampling.<n>On Pl@ntNet300K, BoltNet reaches 0.682 F1-score with 341K parameters (1.37 MB), the highest F1-score among evaluated models below 2 MB.<n>BoltNet is the most consistently efficient model, with the best FPS/W on the GPU and NPU and second-best on the CPU.
  arXiv  Detail & Related papers  (2026-08-12T09:34:52Z)
• Multi-Stage Mamba-Based Architecture for Fast and Scalable Superconducting Qubit Readout [2.7180447022087932]
  In superconducting quantum processors, readout operations are both error-prone and high-latency.<n>We present a multi-stage qubit state discriminator based on the Mamba model.<n>Our model achieves a geometric mean readout fidelity of 0.906, outperforming the best-reported state-of-the-art method.
  arXiv  Detail & Related papers  (2026-07-13T15:12:07Z)
• BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networks [28.844098517315228]
  BitLogic is an end-to-end trainable framework for FPGA-native neural networks.<n>It replaces multiply-accumulate operations with differentiable LUT nodes that map directly to FPGA primitives.<n>It provides native binary computation, sparse connectivity, and efficient hardware realization.
  arXiv  Detail & Related papers  (2026-02-07T06:32:44Z)
• Implementation of high-efficiency, lightweight residual spiking neural network processor based on field-programmable gate arrays [0.49806798459446283]
  This work presents an efficient residual SNN accelerator that combines algorithm and hardware co-design to optimize inference energy efficiency.<n>The proposed processor achieves a classification accuracy of 87.11% on the CIFAR-10 dataset, with an inference time of 3.98 ms per image and an energy efficiency of 183.5 FPS/W.
  arXiv  Detail & Related papers  (2025-12-09T02:08:46Z)
• SpikeLLM: Scaling up Spiking Neural Network to Large Language Models via Saliency-based Spiking [43.275370104552344]
  The human brain is much more energy-efficient than large language models with similar parameters.<n>We propose the first spiking large language model, SpikeLLM.<n>SpikeLLM reduces 11.01% WikiText2 perplexity and improves 2.55% accuracy of common scene reasoning.
  arXiv  Detail & Related papers  (2024-07-05T08:37:17Z)
• ApproxDARTS: Differentiable Neural Architecture Search with Approximate Multipliers [0.24578723416255746]
  We present ApproxDARTS, a neural architecture search (NAS) method enabling the popular differentiable neural architecture search method called DARTS to exploit approximate multipliers. We show that the ApproxDARTS is able to perform a complete architecture search within less than $10$ GPU hours and produce competitive convolutional neural networks (CNN) containing approximate multipliers in convolutional layers.
  arXiv  Detail & Related papers  (2024-04-08T09:54:57Z)
• LogicMP: A Neuro-symbolic Approach for Encoding First-order Logic Constraints [46.60806942245395]
  This paper proposes a novel neural layer, LogicMP, whose layers perform mean-field variational inference over an MLN.<n>It can be plugged into any off-the-shelf neural network to encode FOLCs while retaining modularity and efficiency.<n> Empirical results in three kinds of tasks over graphs, images, and text show that LogicMP outperforms advanced competitors in both performance and efficiency.
  arXiv  Detail & Related papers  (2023-09-27T07:52:30Z)
• An Adaptive Device-Edge Co-Inference Framework Based on Soft Actor-Critic [72.35307086274912]
  High-dimension parameter model and large-scale mathematical calculation restrict execution efficiency, especially for Internet of Things (IoT) devices. We propose a new Deep Reinforcement Learning (DRL)-Soft Actor Critic for discrete (SAC-d), which generates the emphexit point, emphexit point, and emphcompressing bits by soft policy iterations. Based on the latency and accuracy aware reward design, such an computation can well adapt to the complex environment like dynamic wireless channel and arbitrary processing, and is capable of supporting the 5G URL
  arXiv  Detail & Related papers  (2022-01-09T09:31:50Z)
• Neural network relief: a pruning algorithm based on neural activity [47.57448823030151]
  We propose a simple importance-score metric that deactivates unimportant connections. We achieve comparable performance for LeNet architectures on MNIST. The algorithm is not designed to minimize FLOPs when considering current hardware and software implementations.
  arXiv  Detail & Related papers  (2021-09-22T15:33:49Z)
• ANNETTE: Accurate Neural Network Execution Time Estimation with Stacked Models [56.21470608621633]
  We propose a time estimation framework to decouple the architectural search from the target hardware. The proposed methodology extracts a set of models from micro- kernel and multi-layer benchmarks and generates a stacked model for mapping and network execution time estimation. We compare estimation accuracy and fidelity of the generated mixed models, statistical models with the roofline model, and a refined roofline model for evaluation.
  arXiv  Detail & Related papers  (2021-05-07T11:39:05Z)
• NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic [4.119948826527649]
  Field-programmable gate array (FPGA)-based accelerators are gaining traction as a serious contender to replace graphics processing unit/central processing unit-based platforms. This paper presents NullaNet Tiny, a framework for constructing resource and energy-efficient, ultra-low-latency FPGA-based neural network accelerators.
  arXiv  Detail & Related papers  (2021-04-07T00:16:39Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.