Syn2Logic: End-to-End Neuromorphic Design Automation
- URL: http://arxiv.org/abs/2608.25536v1
- Date: Wed, 26 Aug 2026 08:49:02 GMT
- Title: Syn2Logic: End-to-End Neuromorphic Design Automation
- Abstract summary: We see eNDA as a design automation flow that bridges computational neuroscience modeling with traditional EDA flow.<n>We introduce the term, give examples of how it can be implemented, and design a prototype implementation: Syn2Logic.
- Score: 0.0
- License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
- Abstract: In this work, we propose a view on electronic Neuromorphic Design Automation (eNDA), which we see as a design automation flow that bridges computational neuroscience modeling with traditional Electronic Design Automation (EDA) flow. We introduce the term, give examples of how it can be implemented, and design a prototype implementation: Syn2Logic. Syn2Logic is an entire eNDA framework, that allows neuroscientists to model neural behavior using a custom DSL and a compiler that takes the same model description down to synthesizable RTL hardware. We end the paper by applying the eNDA-flow through Syn2Logic to show how to -- without writing a single line of hardware description language (HDL) code-- (i) generate what we believe is the fastest C. elegans accelerator that runs significantly faster than state-of-the-art simulators, (ii) create (to the best of our knowledge) the fastest, most generic neuromorphic sudoku solver that outperforms CP-SAT and SCIP on TOP1465 puzzles, and (iii) create a 5.6 million FPS/Watt accelerator on a tiny FPGA that outperforms existing neuromorphic architectures in terms of speed and energy-efficiency on the MNIST dataset.
Related papers
- Multi-Level Resistive Synapses for On-Chip Neural Networks: A Physics-Based Design of a Memristive Crossbar Fabric with Quasi-Continuous Conductance States [0.766310831583367]
This paper presents a physics-based design of an on-chip neural network with multi-level memristive synapses.<n>We develop a state-variable model and quantify storable sub-levels under thermal noise, drift, and quantized conductance.<n>The result is a hardware-native blueprint for a high-density, analog, in-memory neural processor.
arXiv Detail & Related papers (2026-06-21T18:04:51Z) - YANA: Bridging the Neuromorphic Simulation-to-Hardware Gap [0.559314565030237]
Spiking Neural Networks (SNNs) promise significant advantages over conventional Artificial Neural Networks (ANNs)<n>Yet Another Neuromorphic Accelerator (YANA) provides an accessible hardware and software framework for neuromorphic computing.<n> Deployed on the AMD Kria KR260 platform, a single YANA core utilizes 740 LUTs, 918 registers, 7 BRAMS and 24 URAMs, supporting up to $217$ synapses and $210$ neurons.
arXiv Detail & Related papers (2026-04-03T20:03:11Z) - Towards Cold-Start Drafting and Continual Refining: A Value-Driven Memory Approach with Application to NPU Kernel Synthesis [68.7701048879757]
EvoKernel is a self-evolving agentic framework that automates the lifecycle of kernel synthesis.<n>It learns stage-specific Q-values that prioritize experiences based on their contribution to the current objective.<n>It improves models' correctness from 11.0% to 83.0% and a median speedup of 3.60x over initial drafts.
arXiv Detail & Related papers (2026-03-11T14:57:06Z) - Energy-Efficient Digital Design: A Comparative Study of Event-Driven and Clock-Driven Spiking Neurons [42.170149806080204]
This paper presents a comprehensive evaluation of Spiking Neural Network (SNN) neuron models for hardware acceleration.<n>We begin our investigation in software, rapidly prototyping and testing various SNN models based on different variants of the Leaky Integrate and Fire (LIF) neuron.<n>Our subsequent hardware phase, implemented on FPGA, validates the simulation findings and offers practical insights into design trade offs.
arXiv Detail & Related papers (2025-06-16T09:10:19Z) - A Realistic Simulation Framework for Analog/Digital Neuromorphic Architectures [73.65190161312555]
ARCANA is a software spiking neural network simulator designed to account for the properties of mixed-signal neuromorphic circuits.<n>We show how the results obtained provide a reliable estimate of the behavior of the spiking neural network trained in software, once deployed in hardware.
arXiv Detail & Related papers (2024-09-23T11:16:46Z) - Automatic Generation of Fast and Accurate Performance Models for Deep Neural Network Accelerators [33.18173790144853]
We present an automated generation approach for fast performance models to accurately estimate the latency of a Deep Neural Networks (DNNs)
We modeled representative DNN accelerators such as Gemmini, UltraTrail, Plasticine-derived, and a parameterizable systolic array.
We evaluate only 154 loop kernel iterations to estimate the performance for 4.19 billion instructions achieving a significant speedup.
arXiv Detail & Related papers (2024-09-13T07:27:55Z) - Using the Abstract Computer Architecture Description Language to Model
AI Hardware Accelerators [77.89070422157178]
Manufacturers of AI-integrated products face a critical challenge: selecting an accelerator that aligns with their product's performance requirements.
The Abstract Computer Architecture Description Language (ACADL) is a concise formalization of computer architecture block diagrams.
In this paper, we demonstrate how to use the ACADL to model AI hardware accelerators, use their ACADL description to map DNNs onto them, and explain the timing simulation semantics to gather performance results.
arXiv Detail & Related papers (2024-01-30T19:27:16Z) - Neural Markov Prolog [57.13568543360899]
We propose the language Neural Markov Prolog (NMP) as a means to bridge first order logic and neural network design.
NMP allows for the easy generation and presentation of architectures for images, text, relational databases, or other target data types.
arXiv Detail & Related papers (2023-11-27T21:41:47Z) - CktGNN: Circuit Graph Neural Network for Electronic Design Automation [67.29634073660239]
This paper presents a Circuit Graph Neural Network (CktGNN) that simultaneously automates the circuit topology generation and device sizing.
We introduce Open Circuit Benchmark (OCB), an open-sourced dataset that contains $10$K distinct operational amplifiers.
Our work paves the way toward a learning-based open-sourced design automation for analog circuits.
arXiv Detail & Related papers (2023-08-31T02:20:25Z) - FPGA-optimized Hardware acceleration for Spiking Neural Networks [69.49429223251178]
This work presents the development of a hardware accelerator for an SNN, with off-line training, applied to an image recognition task.
The design targets a Xilinx Artix-7 FPGA, using in total around the 40% of the available hardware resources.
It reduces the classification time by three orders of magnitude, with a small 4.5% impact on the accuracy, if compared to its software, full precision counterpart.
arXiv Detail & Related papers (2022-01-18T13:59:22Z) - DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to
Neuromorphic Hardware [4.273223677453178]
Spiking Neural Networks (SNN) are an emerging computation model, which uses event-driven activation and bio-inspired learning algorithms.
DF Synthesizer is an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware.
arXiv Detail & Related papers (2021-08-04T12:49:37Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.