Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits

• URL: http://arxiv.org/abs/2608.28188v1
• Date: Fri, 28 Aug 2026 10:56:04 GMT
• Title: Beyond Flat Netlist: Hierarchical Graph Representation Learning for Scalable Analysis of Sequential Circuits
• Abstract summary: We introduce DeepSeq3, a novel hierarchical framework that abstracts circuits into a two-level representation.<n>A dual Graph Neural Network (GNN) architecture learns representations at both levels.<n>A state-centric pre-training scheme predicts the reachability between FF states, endowing the model with a deep understanding of temporal behavior.
• Score: 15.582237623722392
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Circuit Representation Learning (CRL) offers a powerful paradigm to guide and optimize core Electronic Design Automation (EDA) tasks, but its practical adoption is hindered by the immense scale of industrial netlists and a failure to explicitly model register-level temporal dynamics. To overcome these barriers, we introduce DeepSeq3, a novel hierarchical framework that abstracts circuits into a two-level representation: fine-grained combinational subgraphs partitioned by flip-flops (FFs), and a high-level Super-Node Graph (SNG) that models the register-transfer structure. A dual Graph Neural Network (GNN) architecture learns representations at both levels, capturing local Boolean logic and global state transitions. Crucially, we introduce a state-centric pre-training scheme that predicts the reachability between FF states, endowing the model with a deep understanding of temporal behavior. Demonstrated on large-scale benchmarks, DeepSeq3's approach yields superior scalability and richer representations, reducing bounded model checking (BMC) solving time by 18% while guaranteeing correctness.

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