Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks

• URL: http://arxiv.org/abs/2107.06064v1
• Date: Fri, 2 Jul 2021 08:50:35 GMT
• Title: Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks
• Authors: Atreya Majumdar, Marc Bocquet, Tifenn Hirtzlin, Axel Laborieux, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean-Michel Portal, Damien Querlioz
• Abstract summary: We present a model of the weak RESET process in hafnium oxide RRAM. We integrate this model within the PyTorch deep learning framework. We use this tool to train Binarized Neural Networks for the MNIST handwritten digit recognition task.
• Score: 0.6745502291821955
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: The implementation of current deep learning training algorithms is power-hungry, owing to data transfer between memory and logic units. Oxide-based RRAMs are outstanding candidates to implement in-memory computing, which is less power-intensive. Their weak RESET regime, is particularly attractive for learning, as it allows tuning the resistance of the devices with remarkable endurance. However, the resistive change behavior in this regime suffers many fluctuations and is particularly challenging to model, especially in a way compatible with tools used for simulating deep learning. In this work, we present a model of the weak RESET process in hafnium oxide RRAM and integrate this model within the PyTorch deep learning framework. Validated on experiments on a hybrid CMOS/RRAM technology, our model reproduces both the noisy progressive behavior and the device-to-device (D2D) variability. We use this tool to train Binarized Neural Networks for the MNIST handwritten digit recognition task and the CIFAR-10 object classification task. We simulate our model with and without various aspects of device imperfections to understand their impact on the training process and identify that the D2D variability is the most detrimental aspect. The framework can be used in the same manner for other types of memories to identify the device imperfections that cause the most degradation, which can, in turn, be used to optimize the devices to reduce the impact of these imperfections.

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