Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learning

• URL: http://arxiv.org/abs/2202.05022v3
• Date: Wed, 4 Jan 2023 08:57:40 GMT
• Title: Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learning
• Authors: Pratik Kumar, Ankita Nandi, Shantanu Chakrabartty, Chetan Singh Thakur
• Abstract summary: Bias-scalable approximate analog computing is attractive for implementing machine learning (ML) processors with distinct power-performance specifications. We demonstrate the implementation of bias-scalable approximate analog computing circuits using the generalization of the margin-propagation principle.
• Score: 6.548257506132353
• License: http://creativecommons.org/licenses/by-nc-sa/4.0/
• Abstract: Bias-scalable analog computing is attractive for implementing machine learning (ML) processors with distinct power-performance specifications. For instance, ML implementations for server workloads are focused on higher computational throughput for faster training, whereas ML implementations for edge devices are focused on energy-efficient inference. In this paper, we demonstrate the implementation of bias-scalable approximate analog computing circuits using the generalization of the margin-propagation principle called shape-based analog computing (S-AC). The resulting S-AC core integrates several near-memory compute elements, which include: (a) non-linear activation functions; (b) inner-product compute circuits; and (c) a mixed-signal compressive memory, all of which can be scaled for performance or power while preserving its functionality. Using measured results from prototypes fabricated in a 180nm CMOS process, we demonstrate that the performance of computing modules remains robust to transistor biasing and variations in temperature. In this paper, we also demonstrate the effect of bias-scalability and computational accuracy on a simple ML regression task.

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