FPGA Hardware Acceleration for Feature-Based Relative Navigation
Applications
- URL: http://arxiv.org/abs/2210.09481v1
- Date: Tue, 18 Oct 2022 00:01:57 GMT
- Title: FPGA Hardware Acceleration for Feature-Based Relative Navigation
Applications
- Authors: Ramchander Rao Bhaskara, Manoranjan Majji
- Abstract summary: This paper develops high-performance avionics for power and resource constrained pose estimation framework.
A Field-Programmable Gate Array (FPGA) based embedded architecture is developed to accelerate estimation of relative pose between the point-clouds.
- Score: 4.812718493682455
- License: http://creativecommons.org/licenses/by/4.0/
- Abstract: Estimation of rigid transformation between two point clouds is a
computationally challenging problem in vision-based relative navigation.
Targeting a real-time navigation solution utilizing point-cloud and image
registration algorithms, this paper develops high-performance avionics for
power and resource constrained pose estimation framework. A Field-Programmable
Gate Array (FPGA) based embedded architecture is developed to accelerate
estimation of relative pose between the point-clouds, aided by image features
that correspond to the individual point sets. At algorithmic level, the pose
estimation method is an adaptation of Optimal Linear Attitude and Translation
Estimator (OLTAE) for relative attitude and translation estimation. At the
architecture level, the proposed embedded solution is a hardware/software
co-design that evaluates the OLTAE computations on the bare-metal hardware for
high-speed state estimation. The finite precision FPGA evaluation of the OLTAE
algorithm is compared with a double-precision evaluation on MATLAB for
performance analysis and error quantification. Implementation results of the
proposed finite-precision OLTAE accelerator demonstrate the high-performance
compute capabilities of the FPGA-based pose estimation while offering relative
numerical errors below 7%.
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