Matching Generalized-Bicycle Codes to Neutral Atoms for Low-Overhead Fault-Tolerance

• URL: http://arxiv.org/abs/2311.16980v2
• Date: Sun, 3 Mar 2024 16:21:35 GMT
• Title: Matching Generalized-Bicycle Codes to Neutral Atoms for Low-Overhead Fault-Tolerance
• Authors: Joshua Viszlai, Willers Yang, Sophia Fuhui Lin, Junyu Liu, Natalia Nottingham, Jonathan M. Baker, Frederic T. Chong
• Abstract summary: We present a protocol for implementing a restricted set of space-efficient quantum error correcting codes in atom arrays. This protocol enables generalized-bicycle codes that require up to 10x fewer physical qubits than surface codes. We also evaluate a proof-of-concept quantum memory hier- archy where generalized-bicycle codes are used in conjunction with surface codes for general computation.
• Score: 7.718509743812828
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Despite the necessity of fault-tolerant quantum sys- tems built on error correcting codes, many popular codes, such as the surface code, have prohibitively large qubit costs. In this work we present a protocol for efficiently implementing a restricted set of space-efficient quantum error correcting (QEC) codes in atom arrays. This protocol enables generalized-bicycle codes that require up to 10x fewer physical qubits than surface codes. Additionally, our protocol enables logical cycles that are 2-3x faster than more general solutions for implementing space- efficient QEC codes in atom arrays. We also evaluate a proof-of-concept quantum memory hier- archy where generalized-bicycle codes are used in conjunction with surface codes for general computation. Through a detailed compilation methodology, we estimate the costs of key fault- tolerant benchmarks in a hierarchical architecture versus a state-of-the-art surface code only architecture. Overall, we find the spatial savings of generalized-bicycle codes outweigh the overhead of loading and storing qubits, motivating the feasibility of a quantum memory hierarchy in practice. Through sensitivity studies, we also identify key program-level and hardware-level features for using a hierarchical architecture.

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