CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks

• URL: http://arxiv.org/abs/2401.07142v1
• Date: Sat, 13 Jan 2024 19:09:22 GMT
• Title: CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks
• Authors: Levent Aksoy, Muhammad Yasin, Samuel Pagliarini,
• Abstract summary: State-of-the-art logic locking techniques, including the prominent corrupt and correct (CAC) technique, are resilient to satisfiability (SAT)-based and removal attacks. This paper introduces an improved version of CAC, called CAC 2.0, which increases the search space of structural analysis attacks using obfuscation. This paper also introduces an open source logic locking tool, called HIID, equipped with well-known techniques including CAC 2.0.
• Score: 2.949446809950691
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Logic locking proposed to protect integrated circuits from serious hardware threats has been studied extensively over a decade. In these years, many efficient logic locking techniques have been proven to be broken. The state-of-the-art logic locking techniques, including the prominent corrupt and correct (CAC) technique, are resilient to satisfiability (SAT)-based and removal attacks, but vulnerable to structural analysis attacks. To overcome this drawback, this paper introduces an improved version of CAC, called CAC 2.0, which increases the search space of structural analysis attacks using obfuscation. To do so, CAC 2.0 locks the original circuit twice, one after another, on different nodes with different number of protected primary inputs using CAC, while hiding original protected primary inputs among decoy primary inputs. This paper also introduces an open source logic locking tool, called HIID, equipped with well-known techniques including CAC 2.0. Our experiments show that CAC 2.0 is resilient to existing SAT-based, removal, and structural analysis attacks. To achieve this, it increases the number of key inputs at most 4x and the gate-level area between 30.2% and 0.8% on circuits with low and high complexity with respect to CAC.

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