A Micro Architectural Events Aware Real-Time Embedded System Fault Injector

• URL: http://arxiv.org/abs/2401.08397v2
• Date: Tue, 11 Jun 2024 08:44:00 GMT
• Title: A Micro Architectural Events Aware Real-Time Embedded System Fault Injector
• Authors: Enrico Magliano, Alessio Carpegna, Alessadro Savino, Stefano Di Carlo,
• Abstract summary: This paper introduces a novel fault injector designed to facilitate the monitoring, aggregation, and examination of micro-architectural events. The methodology targets bit-flipping within the memory system, affecting CPU registers and RAM. The outcomes of these fault injections enable a thorough analysis of the impact of soft errors and establish a robust correlation between the identified faults and the essential timing predictability demanded by SACRES.
• Score: 0.12187048691454236
• License: http://creativecommons.org/licenses/by-nc-sa/4.0/
• Abstract: In contemporary times, the increasing complexity of the system poses significant challenges to the reliability, trustworthiness, and security of the SACRES. Key issues include the susceptibility to phenomena such as instantaneous voltage spikes, electromagnetic interference, neutron strikes, and out-of-range temperatures. These factors can induce switch state changes in transistors, resulting in bit-flipping, soft errors, and transient corruption of stored data in memory. The occurrence of soft errors, in turn, may lead to system faults that can propel the system into a hazardous state. Particularly in critical sectors like automotive, avionics, or aerospace, such malfunctions can have real-world implications, potentially causing harm to individuals. This paper introduces a novel fault injector designed to facilitate the monitoring, aggregation, and examination of micro-architectural events. This is achieved by harnessing the microprocessor's PMU and the debugging interface, specifically focusing on ensuring the repeatability of fault injections. The fault injection methodology targets bit-flipping within the memory system, affecting CPU registers and RAM. The outcomes of these fault injections enable a thorough analysis of the impact of soft errors and establish a robust correlation between the identified faults and the essential timing predictability demanded by SACRES.

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