Fast ML-driven Analog Circuit Layout using Reinforcement Learning and Steiner Trees
- URL: http://arxiv.org/abs/2405.16951v1
- Date: Mon, 27 May 2024 08:42:42 GMT
- Title: Fast ML-driven Analog Circuit Layout using Reinforcement Learning and Steiner Trees
- Authors: Davide Basso, Luca Bortolussi, Mirjana Videnovic-Misic, Husni Habal,
- Abstract summary: This paper presents an artificial intelligence driven methodology to reduce the bottleneck often encountered in the analog ICs layout phase.
We frame the floorplanning problem as a Markov Decision Process and leverage reinforcement learning for automatic placement generation under established topological constraints.
- Score: 0.3749861135832073
- License: http://creativecommons.org/licenses/by-nc-nd/4.0/
- Abstract: This paper presents an artificial intelligence driven methodology to reduce the bottleneck often encountered in the analog ICs layout phase. We frame the floorplanning problem as a Markov Decision Process and leverage reinforcement learning for automatic placement generation under established topological constraints. Consequently, we introduce Steiner tree-based methods for the global routing step and generate guiding paths to be used to connect every circuit block. Finally, by integrating these solutions into a procedural generation framework, we present a unified pipeline that bridges the divide between circuit design and verification steps. Experimental results demonstrate the efficacy in generating complete layouts, eventually reducing runtimes to 1.5% compared to manual efforts.
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